Design of Two-Stage Op-Amp using Cadence Tools

📌 Project Information

• Project Title: Design of Two-Stage Op-Amp using Cadence Tools
• Author: Abhinav K R

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🎯 Objective

• To design a two-stage op-amp using Cadence Virtuoso.
• Implement the circuit using Virtuoso Schematic Editor.
• Select appropriate transistor sizing and biasing.
• Perform layout design and verification to ensure correctness and manufacturability.

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💡 Motivation

• Amplifiers are fundamental components in analog circuits, used in communication, signal processing, and sensor applications.
• High-gain amplifiers are essential for boosting weak signals.
• Single-stage amplifiers often fail to provide high gain and sufficient bandwidth simultaneously.
• Stability and impedance matching are challenging in single-stage designs → motivating the need for a two-stage op-amp.

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🛠️ Tools Used

• Cadence Virtuoso (schematic, layout, simulation)
• Schematic Design & Simulation Tools
• Layout Design & Verification Tools

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📐 Methodology

1. Invoke Cadence Virtuoso tool.
2. Create library and attach gpdk45 technology.
3. Design schematic of two-stage op-amp.
4. Form test symbol and design test circuit.
5. Launch ADE L for analysis.
6. Perform Transient, DC, and AC analysis.
7. Implement layout design.
8. Verify using DRC and LVS checks.

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🔬 Simulation Results

Transient Analysis

• Stop Time: 100u
• Accuracy: Moderate
• Vin = 1.3V → Vout = 1.30143V

DC Analysis

• Verified biasing and operation.

AC Analysis

• Sweep Range: 1 Hz – 10 GHz (logarithmic, 10 points/decade)
• Unity Gain Bandwidth (GBW): 39.7977 MHz
• 3 dB Bandwidth: 36.8121 kHz
• Phase Margin: 66.71°
• Gain: 62 dB

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🖼️ Layout Design & Verification

• Design Rule Check (DRC): Ensures manufacturability by checking layer widths, spacings, etc.
• Layout vs Schematic (LVS): Confirms that layout matches schematic netlist.

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📖 References

1. Sharvani Vanaparthi, Dr. Mahesh Mudavath, Dr. Pankaj Rangaree, Design and Implementation of 45nm Operational Amplifier, IJRTI, Vol. 7, Issue 9, 2022.
2. Sonu Kumar et al., Design of CMOS Operational Amplifier in 180nm Technology, IJIRCCE, Vol. 5, Issue 4, 2017.
3. R Bharath Reddy, Shilpa K Gowda, Design and Analysis of CMOS Two-Stage Op-Amp in 180nm and 45nm Technology, IJERT, Vol. 4, Issue 5, 2015.
4. Praful Ranjan et al., Design and Analysis of Two-Stage Op-Amp for Bio-Medical Application, IJ Wearable Device, Vol. 3, No. 1, 2016.
5. Shruthi Suman, Two-Stage CMOS Operational Amplifier: Analysis and Design, MU International Journal of Computing and Engineering Research, 2019.

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⚡ Requirements

To run this project, you need access to:

• Cadence Virtuoso (with gpdk45 or similar PDK)
• Linux environment (for Cadence setup)

List of dependencies (requirements.txt style for reference):

cadence-virtuoso
gpdk45
spectre-simulator