feat(fpga): Vivado CI pipeline for gf16_heartbeat_uart_top (UART telemetry on K20)#604
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feat(fpga): Vivado CI pipeline for gf16_heartbeat_uart_top (UART telemetry on K20)#604gHashTag wants to merge 1 commit into
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- fpga/vivado/uart/build.tcl: batch TCL script (in-memory project, xc7a100tfgg676-1, synth→opt→place→route→write_bitstream) - fpga/vivado/uart/gf16_heartbeat_uart_top.v: 115200-baud UART TX telemetry top (282 lines, heartbeat + GF(2^4) dot4 result) - fpga/vivado/uart/gf16_heartbeat_uart_top.xdc: pin constraints (K20=uart_tx, LEDs R23/T23/J26, bitstream config) - .github/workflows/vivado-build.yml: CI workflow triggering on push to feat/vivado-ci, workflow_dispatch, and PRs labelled build:vivado; uploads .bit + .rpt artifacts; SHA-256 in step summary - fpga/vivado/uart/Dockerfile: self-hosted runner base image (Vivado volume-mounted from host, Ubuntu 22.04) - fpga/vivado/uart/SETUP_RUNNER.md: end-to-end runner setup guide - fpga/vivado/uart/README.md: directory overview and quick-start No .sh or .py scripts added (L7 compliance).
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Vivado CI pipeline for UART-telemetry bitstream
Adds a Vivado batch build pipeline for
gf16_heartbeat_uart_topso we can produce a.bitwith 115200-baud UART TX telemetry on K20, on top of the silicon-verifiedgf16_heartbeat_topbaseline (LEDs blinking confirmed via JTAG SRAM load).What's in here
fpga/vivado/uart/build.tcl— in-memory Vivado project (xc7a100tfgg676-1), synth → opt → place → route →write_bitstream, producesbuild/output/*.bit+ timing/utilisation reportsgf16_heartbeat_uart_top.v— heartbeat +uart_tx_8n1(115200, DIV=564) + frame builder emitting"T:HH R:HHHH\r\n"on layer transitions, clocked fromSTARTUPE2.CFGMCLK(~65 MHz)gf16_heartbeat_uart_top.xdc— LEDsR23/T23/J26(active-LOW),uart_txonK20(J2 pin 5),BITSTREAM.STARTUP.STARTUPCLK JtagClkDockerfile— Ubuntu 22.04 base, expects/opt/Xilinx/Vivado/2023.2bind-mounted from hostSETUP_RUNNER.md— AMD account → Vivado 2023.2 Standard Edition →/opt/Xilinxinstall → license → runner registration with labelsself-hosted,linux,vivado. Includeslibtinfo5fix for Ubuntu 22.04.README.md/SUMMARY.md— overview + next-steps.github/workflows/vivado-build.ymlfeat/vivado-ci,workflow_dispatch, PRs with labelbuild:vivado[self-hosted, linux, vivado], 30 min timeout$XILINX_VIVADO/bin, runsvivado -mode batch -nojournal -nolog -source build.tcl.bit+.rptartifacts; SHA-256 to step summary.sh/.py(L7 compliant)Why a new workflow (not extending the existing one)
.github/workflows/fpga-build.ymlis the openXC7 "Zero Vivado" path — it does not modelSTARTUPE2, which is why the openXC7-builtblink_j26.bitfailed on real silicon (STAT=0x4000190C, DONE=0) while the Vivado-builtgf16_heartbeat_top.bitworks (STAT=0x401079FC, DONE=1, LEDs blink). Vivado CI is additive, not a replacement.Expected CI state on merge
CI will fail until a self-hosted runner with Vivado 2023.2 is registered (
SETUP_RUNNER.mdcovers this). The workflow is gated behindworkflow_dispatch+ thebuild:vivadoPR label so it doesn't block other CI.Hardware target (verified)
QMTech XC7A100T Wukong V1, FGG676 — same board on which
gf16_heartbeat_top.bitis currently blinking via JTAG SRAM. After CI produces the UART bitstream, the plan is: artifact → SRAM load → wire FT232RL (VID0403:6001) to K20/GND → read tok/s on host.Compliance
.sh/.pyCloses #592already shipped onfeat/dlc10-rust@a301834d; this PR is independent infrastructure (no ticket — Vivado-CI tracking can be opened separately if needed)