SystemC

.github/workflows/general.yml

@@ -61,17 +61,29 @@ jobs:
       - name: Install software - Icarus Verilog
         run: tool/gh_actions/install_iverilog.sh
 
+      - name: Install software - Accellera SystemC
+        run: tool/gh_actions/install_systemc.sh
+
+      - name: Pre-build SystemC PCH and Makefile
+        run: tool/gh_actions/setup_systemc_pch.sh
+
       - name: Run project tests
         run: tool/gh_actions/run_tests.sh
 
+      - name: Run SystemC tests
+        run: dart test test/systemc_vector_test.dart
+
       - name: Check temporary test files
         run: tool/gh_actions/check_tmp_test.sh
 
       # https://github.com/devcontainers/ci/blob/main/docs/github-action.md
       - name: Build dev container and run tests in it
         uses: devcontainers/ci@v0.3
         with:
-          runCmd: tool/gh_actions/run_tests.sh
+          runCmd: |
+            tool/gh_actions/run_tests.sh
+            dart test test/systemc_vector_test.dart
+            tool/gh_actions/check_tmp_test.sh
 
   deploy-documentation:
     name: Deploy Documentation

README.md

@@ -44,7 +44,7 @@ You can also open this repository in a GitHub Codespace to run the example in yo
 - **Simple and fast build**, free of complex build systems and EDA vendor tools
 - Can use the excellent pub.dev **package manager** and all the packages it has to offer
 - Built-in event-based **fast simulator** with **4-value** (0, 1, X, and Z) support and a **waveform dumper** to .vcd file format
-- Conversion of modules to equivalent, human-readable, structurally similar **SystemVerilog** for integration or downstream tool consumption
+- Conversion of modules to equivalent, human-readable, structurally similar **SystemVerilog** and **SystemC** for integration or downstream tool consumption
 - **Run-time dynamic** module port definitions (numbers, names, widths, etc.) and internal module logic, including recursive module contents
 - Leverage the [ROHD Hardware Component Library (ROHD-HCL)](https://github.com/intel/rohd-hcl) with reusable and configurable design and verification components.
 - Simple, free, **open source tool stack** without any headaches from library dependencies, file ordering, elaboration/analysis options, +defines, etc.

dart_test.yaml

@@ -0,0 +1,15 @@
+# Test configuration for ROHD.
+#
+# To exclude FFI-dependent tests (e.g. in CI without native code support):
+#   dart test --preset no-ffi
+#
+# To run all tests including FFI (requires native shared libraries):
+#   dart test
+
+tags:
+  ffi:
+    # Tests requiring dart:ffi and native shared libraries.
+
+presets:
+  no-ffi:
+    exclude_tags: ffi

doc/architecture.md

@@ -24,7 +24,7 @@ The `Simulator` acts as a statically accessible driver of the overall simulation
 
 ### Synthesizer
 
-A separate type of object responsible for taking a `Module` and converting it to some output, such as SystemVerilog.
+A separate type of object responsible for taking a `Module` and converting it to some output, such as SystemVerilog or SystemC.
 
 ## Organization
 
@@ -44,7 +44,7 @@ Contains a collection of `Module` implementations that can be used as primitive
 
 ### Synthesizers
 
-Contains logic for synthesizing `Module`s into some output. It is structured to maximize reusability across different output types (including those not yet supported).
+Contains logic for synthesizing `Module`s into some output (e.g. SystemVerilog, SystemC). It is structured to maximize reusability across different output types.
 
 ### Utilities
 

doc/tutorials/chapter_6/answers/exercise_2_n_bit_subtractor.dart

@@ -7,7 +7,6 @@ import '../../chapter_3/answers/helper.dart';
 import '../../chapter_5/answers/full_subtractor.dart';
 
 class FullSubtractorComb extends FullSubtractor {
-  @override
   FullSubtractorComb(super.a, super.b, super.borrowIn) {
     // Declare input and output
     final a = input('a');

doc/user_guide/_docs/A21-generation.md

@@ -5,7 +5,7 @@ last_modified_at: 2023-11-13
 toc: true
 ---
 
-Hardware in ROHD is convertible to an output format via `Synthesizer`s, the most popular of which is SystemVerilog. Hardware in ROHD can be converted to logically equivalent, human-readable SystemVerilog with structure, hierarchy, ports, and names maintained.
+Hardware in ROHD is convertible to an output format via `Synthesizer`s. The most popular output format is SystemVerilog, with SystemC also available. Hardware in ROHD can be converted to logically equivalent, human-readable SystemVerilog or SystemC with structure, hierarchy, ports, and names maintained.
 
 The simplest way to generate SystemVerilog is with the helper method `generateSynth` in `Module`:
 
@@ -28,6 +28,26 @@ void main() async {
 
 The `generateSynth` function will return a `String` with the SystemVerilog `module` definitions for the top-level it is called on, as well as any sub-modules (recursively).  You can dump the entire contents to a file and use it anywhere you would any other SystemVerilog.
 
+## SystemC generation
+
+ROHD can also generate SystemC (C++ with the SystemC library) from the same hardware description. Use the `generateSystemC` helper method:
+
+```dart
+void main() async {
+    final myModule = MyModule();
+    await myModule.build();
+
+    final generatedSc = myModule.generateSystemC();
+
+    // write it to a file
+    File('myHardware.h').writeAsStringSync(generatedSc);
+}
+```
+
+The generated SystemC uses `SC_MODULE`, `SC_METHOD`, and `SC_CTHREAD` constructs. Combinational logic becomes `SC_METHOD` processes, sequential logic (flip-flops and `Sequential` blocks) sharing the same clock and reset are consolidated into a single `SC_CTHREAD`, and sub-modules are instantiated with port bindings. All signal types map to SystemC equivalents (`bool`, `sc_uint<N>`, `sc_biguint<N>`).
+
+For more control over SystemC generation, use `SynthBuilder` with `SystemCSynthesizer()` directly.
+
 ## Controlling naming
 
 ### Modules

doc/user_guide/_get-started/01-overview.md

@@ -19,7 +19,7 @@ Features of ROHD include:
 - **Simple and fast build**, free of complex build systems and EDA vendor tools
 - Can use the excellent pub.dev **package manager** and all the packages it has to offer
 - Built-in event-based **fast simulator** with **4-value** (0, 1, X, and Z) support and a **waveform dumper** to .vcd file format
-- Conversion of modules to equivalent, human-readable, structurally similar **SystemVerilog** for integration or downstream tool consumption
+- Conversion of modules to equivalent, human-readable, structurally similar **SystemVerilog** and **SystemC** for integration or downstream tool consumption
 - **Run-time dynamic** module port definitions (numbers, names, widths, etc.) and internal module logic, including recursive module contents
 - Leverage the [ROHD Hardware Component Library (ROHD-HCL)](https://github.com/intel/rohd-hcl) with reusable and configurable design and verification components.
 - Simple, free, **open source tool stack** without any headaches from library dependencies, file ordering, elaboration/analysis options, +defines, etc.

lib/rohd.dart

@@ -1,6 +1,7 @@
 // Copyright (C) 2021-2023 Intel Corporation
 // SPDX-License-Identifier: BSD-3-Clause
 
+export 'src/diagnostics/module_services.dart';
 export 'src/exceptions/exceptions.dart';
 export 'src/external.dart';
 export 'src/finite_state_machine.dart';

lib/src/diagnostics/module_services.dart

@@ -0,0 +1,78 @@
+// Copyright (C) 2026 Intel Corporation
+// SPDX-License-Identifier: BSD-3-Clause
+//
+// module_services.dart
+// Singleton service registry for DevTools integration.
+//
+// 2026 April 25
+// Author: Desmond Kirkpatrick <desmond.a.kirkpatrick@intel.com>
+
+import 'dart:convert';
+
+import 'package:rohd/rohd.dart';
+import 'package:rohd/src/diagnostics/inspector_service.dart';
+
+/// Singleton service registry that provides a unified query surface for
+/// DevTools and other inspection tools.
+///
+/// Services register themselves here on construction; DevTools evaluates
+/// getters on [instance] via `EvalOnDartLibrary` to pull data.
+///
+/// **Auto-registered:**
+///  - [rootModule] / [hierarchyJSON] — set by [Module.build].
+///
+/// **Opt-in (registered by service constructors):**
+///  - [svService] — SystemVerilog synthesis results.
+///
+/// Additional services (netlist, trace, waveform) can be added by setting
+/// the corresponding field after construction.
+class ModuleServices {
+  ModuleServices._();
+
+  /// The singleton instance.
+  static final ModuleServices instance = ModuleServices._();
+
+  // ─── Hierarchy (auto-registered by Module.build) ──────────────
+
+  /// The most recently built top-level [Module].
+  ///
+  /// Set automatically at the end of [Module.build].
+  Module? rootModule;
+
+  /// Returns the module hierarchy as a JSON string.
+  ///
+  /// DevTools evaluates this via `EvalOnDartLibrary` to display
+  /// the module hierarchy.
+  String get hierarchyJSON {
+    ModuleTree.rootModuleInstance = rootModule;
+    return ModuleTree.instance.hierarchyJSON;
+  }
+
+  /// Returns the primary inspector JSON for DevTools.
+  ///
+  /// Returns the hierarchy JSON.  Downstream branches (e.g. netlist) may
+  /// override this to return richer data when available.
+  String get inspectorJSON => hierarchyJSON;
+
+  // ─── SystemVerilog service (opt-in) ───────────────────────────
+
+  /// The active [SvService], if one has been registered.
+  SvService? svService;
+
+  /// Returns SV synthesis metadata as JSON, or an unavailable status.
+  String get svJSON =>
+      svService != null ? jsonEncode(svService!.toJson()) : _unavailable('sv');
+
+  // ─── Helpers ──────────────────────────────────────────────────
+
+  static String _unavailable(String service) => jsonEncode(<String, String>{
+        'status': 'unavailable',
+        'reason': '$service service not registered',
+      });
+
+  /// Resets all services.  Intended for test teardown.
+  void reset() {
+    rootModule = null;
+    svService = null;
+  }
+}

lib/src/module.dart

@@ -1,4 +1,4 @@
-// Copyright (C) 2021-2025 Intel Corporation
+// Copyright (C) 2021-2026 Intel Corporation
 // SPDX-License-Identifier: BSD-3-Clause
 //
 // module.dart
@@ -11,11 +11,10 @@ import 'dart:async';
 import 'dart:collection';
 
 import 'package:meta/meta.dart';
-
 import 'package:rohd/rohd.dart';
 import 'package:rohd/src/collections/traverseable_collection.dart';
-import 'package:rohd/src/diagnostics/inspector_service.dart';
 import 'package:rohd/src/utilities/config.dart';
+import 'package:rohd/src/utilities/namer.dart';
 import 'package:rohd/src/utilities/sanitizer.dart';
 import 'package:rohd/src/utilities/timestamper.dart';
 import 'package:rohd/src/utilities/uniquifier.dart';
@@ -52,6 +51,22 @@ abstract class Module {
   /// An internal mapping of input names to their sources to this [Module].
   late final Map<String, Logic> _inputSources = {};
 
+  // ─── Central naming (Namer) ─────────────────────────────────────
+
+  /// Central namer that owns both the signal and instance namespaces.
+  /// Initialized lazily on first access (after build).
+  @internal
+  late final Namer namer = _createNamer();
+
+  Namer _createNamer() {
+    assert(hasBuilt, 'Module must be built before canonical names are bound.');
+    return Namer.forModule(
+      inputs: _inputs,
+      outputs: _outputs,
+      inOuts: _inOuts,
+    );
+  }
+
   /// An internal mapping of inOut names to their sources to this [Module].
   late final Map<String, Logic> _inOutSources = {};
 
@@ -317,7 +332,7 @@ abstract class Module {
 
     _hasBuilt = true;
 
-    ModuleTree.rootModuleInstance = this;
+    ModuleServices.instance.rootModule = this;
   }
 
   /// Confirms that the post-[build] hierarchy is valid.
@@ -1131,6 +1146,27 @@ abstract class Module {
             .getSynthFileContents()
             .join('\n\n////////////////////\n\n');
   }
+
+  /// Returns a synthesized SystemC version of this [Module].
+  ///
+  /// Generates SystemC code that is equivalent to the hardware described by
+  /// this module, using the same naming strategy as [generateSynth].
+  String generateSystemC() {
+    if (!_hasBuilt) {
+      throw ModuleNotBuiltException(this);
+    }
+
+    final synthBuilder = SynthBuilder(this, SystemCSynthesizer());
+    final moduleContents =
+        synthBuilder.getSynthFileContents().map((e) => e.contents).join('\n');
+    return '// Generated by ROHD - www.github.com/intel/rohd\n'
+        '// Generation time: ${Timestamper.stamp()}\n'
+        '// ROHD Version: ${Config.version}\n'
+        '\n'
+        '#include <systemc.h>\n'
+        '\n'
+        '$moduleContents';
+  }
 }
 
 extension on LogicStructure {

lib/src/modules/conditionals/flop.dart

@@ -88,6 +88,11 @@ class FlipFlop extends Module with SystemVerilog {
   /// Only initialized if a constant value is provided.
   late LogicValue _resetValueConst;
 
+  /// Returns the constant reset value if one was provided, or null if the
+  /// reset value is a port or no reset exists.
+  LogicValue? get constantResetValue =>
+      _reset != null && _resetValuePort == null ? _resetValueConst : null;
+
   /// Indicates whether provided `reset` signals should be treated as an async
   /// reset. If no `reset` is provided, this will have no effect.
   final bool asyncReset;

lib/src/modules/conditionals/sequential.dart

@@ -135,6 +135,14 @@ class Sequential extends Always {
   /// The input edge triggers used in this block.
   final List<_SequentialTrigger> _triggers = [];
 
+  /// Returns the edge polarity for each trigger input port.
+  ///
+  /// Each entry pairs the trigger input port name with whether the trigger
+  /// fires on a positive edge (`true`) or negative edge (`false`).
+  List<({String portName, bool isPosedge})> get triggerEdges => _triggers
+      .map((t) => (portName: t.signal.name, isPosedge: t.isPosedge))
+      .toList();
+
   /// When `false`, an [SignalRedrivenException] will be thrown during
   /// simulation if the same signal is driven multiple times within this
   /// [Sequential].

lib/src/synthesizers/synth_builder.dart

@@ -1,4 +1,4 @@
-// Copyright (C) 2021-2025 Intel Corporation
+// Copyright (C) 2021-2026 Intel Corporation
 // SPDX-License-Identifier: BSD-3-Clause
 //
 // synth_builder.dart

lib/src/synthesizers/synthesizer.dart

@@ -1,12 +1,11 @@
-// Copyright (C) 2021-2023 Intel Corporation
+// Copyright (C) 2021-2026 Intel Corporation
 // SPDX-License-Identifier: BSD-3-Clause
 //
 // synthesizer.dart
 // Generic definition for something that synthesizes output files
 //
 // 2021 August 26
 // Author: Max Korbel <max.korbel@intel.com>
-//
 
 import 'package:rohd/rohd.dart';
 

lib/src/synthesizers/synthesizers.dart

@@ -5,4 +5,5 @@ export 'synth_builder.dart';
 export 'synth_file_contents.dart';
 export 'synthesis_result.dart';
 export 'synthesizer.dart';
+export 'systemc/systemc.dart';
 export 'systemverilog/systemverilog.dart';

lib/src/synthesizers/systemc/systemc.dart

@@ -0,0 +1,29 @@
+// Copyright (C) 2021-2026 Intel Corporation
+// SPDX-License-Identifier: BSD-3-Clause
+//
+// systemc_synthesizer.dart
+// Definition for SystemC Synthesizer
+//
+// 2026 May
+// Author: Desmond A. Kirkpatrick <desmond.a.kirkpatrick@intel.com>
+
+import 'package:rohd/rohd.dart';
+import 'package:rohd/src/synthesizers/systemc/systemc_synthesis_result.dart';
+
+/// A [Synthesizer] which generates equivalent SystemC as the given [Module].
+///
+/// Attempts to maintain signal naming and structure as much as possible,
+/// using the same naming strategy as the SystemVerilog synthesizer.
+class SystemCSynthesizer extends Synthesizer {
+  @override
+  bool generatesDefinition(Module module) =>
+      // ignore: deprecated_member_use_from_same_package
+      !((module is CustomSystemVerilog) ||
+          (module is SystemVerilog &&
+              module.generatedDefinitionType == DefinitionGenerationType.none));
+
+  @override
+  SynthesisResult synthesize(Module module,
+          String Function(Module module) getInstanceTypeOfModule) =>
+      SystemCSynthesisResult(module, getInstanceTypeOfModule);
+}