feat(lance-linalg): runtime SIMD dispatch for pre-Haswell x86_64 from-source builds

[tobocop2]

Tracks #6618. On x86_64 CPUs without AVX2 — Sandy Bridge / Ivy Bridge / Westmere on Intel, Bulldozer / Piledriver / Steamroller on AMD — import lancedb SIGILLs because the wheel bakes AVX2 + FMA into every compiled function with no runtime guard. numpy and pyarrow handle the same hardware via runtime CPU dispatch.

Summary

• Adds 5-tier runtime SIMD dispatch (scalar / AVX / AVX+FMA / AVX2+FMA / AVX-512) to the f32/f64 hot kernels in lance-linalg::distance::{cosine, dot, l2, norm_l2}. Same match *SIMD_SUPPORT + mod x86 { #[target_feature] pub unsafe fn ... } shape as dot_u8.rs / cosine_u8.rs / l2_u8.rs. Where the AVX2 and AVX+FMA kernel bodies use no AVX2-specific intrinsics, the dispatch matches Avx2 | AvxFma to a shared kernel.
• Adds lance.simd_info() Python introspection mirroring pyarrow.runtime_info() so users can verify which tier the runtime selected.
• Adds a qemu-pre-haswell CI job that builds with RUSTFLAGS="-C target-cpu=x86-64-v2" (env-var-scoped to that one job — workspace .cargo/config.toml is unchanged) and runs lance-linalg lib tests under qemu-x86_64 -cpu Nehalem.
• Documents the legacy build path in CONTRIBUTING.md: RUSTFLAGS="-C target-cpu=x86-64-v2" cargo build --release.

Per westonpace's review on lancedb/lancedb#3324, the workspace baseline stays at target-cpu=haswell. Modern wheels are unchanged; legacy users opt into the lower baseline at build time.

Benchmark

The AVX2 path on modern hardware is preserved as one of the per-tier kernels and the workspace baseline still bakes AVX2 into surrounding code, so by construction the modern compile is unchanged. Numbers still pending — Codespace's 30-min idle timeout killed my last full cargo bench -p lance-linalg --bench {cosine,dot,l2,norm_l2} run mid-suite (even with nohup — the VM itself sleeps). If anyone can recommend a free resource that holds a benchmark for ~1 hour, or a maintainer-preferred narrower bench shape, I'd appreciate the pointer.

Pre-Haswell verification on Sandy Bridge Xeon E5-2609 (the hardware the published wheel SIGILLs on) via the companion lancedb wheel build: pre-PR pip install lancedb SIGILLs at import; post-PR a from-source build with the documented RUSTFLAGS override produces a wheel where import + table-create + vector-search all work at the AVX tier. PASS output in tobocop2/lancedb#2.

Test plan

• cargo test -p lance-linalg --lib — 83/83 on aarch64 dev box
• cargo clippy --all-targets -- -D warnings clean; cargo fmt --check clean; Cargo.lock unchanged
• 11 proptest cases verifying scalar↔SIMD bit-for-bit equivalence per tier per kernel; gated on is_x86_feature_detected!() so each runs on hosts that can execute its tier
• SIGILL repro confirmed gone on Sandy Bridge Xeon E5-2609 with the documented RUSTFLAGS override
• qemu-pre-haswell CI gate green (lights up when this PR runs CI)
• Modern-hardware bench delta posted

---

To be transparent: this isn't my domain of expertise and the implementation is AI-generated — I stuck to the existing mod x86 { #[target_feature] } precedent and verified end-to-end on the failing hardware, but wanted to be upfront. Happy to roll in feedback.

[claude]

Claude Code Review

This pull request is from a fork — automated review is disabled. A repository maintainer can comment @claude review to run a one-time review.

[stumpylog]

Benchmarked this PR on two modern x86_64 boxes (the "no slowdown on newer hardware" question). As-is it regresses the f32 cosine batch path on AVX2-only CPUs; a small refinement fixes that while keeping the AVX-512 win.

cargo bench -p lance-linalg --bench cosine, criterion, same-session base→PR→fix (Cosine(f32, scalar) is a build-independent control ≈ 0% on clean runs). auto-vectorized = cosine_distance_batch dim 1024; simd,f32x8 = dim 8.

PR as-is vs base:

	Broadwell (AVX2)	Zen 4 (AVX-512)
dim 1024	+24%	−6%
dim 8	+36%	+78%

Cause: f32::cosine_batch does the match *SIMD_SUPPORT + a #[target_feature] call per vector. On a wheel already built with target-cpu=haswell, that's pure overhead vs the pre-PR inlined f32x16/f32x8 kernel.

Refinement: gate the dispatch on #[cfg(target_feature = "avx2")] — AVX2-baseline builds use the inlined (byte-identical to pre-PR) kernels with no per-vector dispatch, and dispatch to AVX-512 once per batch, large dims only (a masked 512-bit load loses to a plain AVX2 load at 8 lanes). Sub-AVX2 builds keep your runtime path.

After (fix vs base):

	Broadwell (AVX2)	Zen 4 (AVX-512)
dim 1024	+6%	−7%
dim 8	flat	−3%

Fast by default, AVX-512 still wins where it helps.

Notes: the +6% at dim 1024 on AVX2 is a codegen-unit artifact (the kernel there is byte-identical to pre-PR), not the dispatch path. I only reworked f32 cosine — dot/l2/norm_l2 have the same per-vector shape and likely the same regression. Branch: https://github.com/stumpylog/lance/tree/cosine-batch-dispatch-fix — happy to PR it against your branch.

(Downstream context: paperless-ngx/paperless-ngx#12970.)

[tobocop2]

I'd love the PR to my branch! Thank you!!!

…

On Wed, Jun 10, 2026, 4:01 PM Trenton H ***@***.***> wrote: *stumpylog* left a comment (lance-format/lance#6630) <#6630 (comment)> Benchmarked this PR on two modern x86_64 boxes (the "no slowdown on newer hardware" question). As-is it regresses the f32 cosine *batch* path on AVX2-only CPUs; a small refinement fixes that while keeping the AVX-512 win. cargo bench -p lance-linalg --bench cosine, criterion, same-session base→PR→fix (Cosine(f32, scalar) is a build-independent control ≈ 0% on clean runs). auto-vectorized = cosine_distance_batch dim 1024; simd,f32x8 = dim 8. *PR as-is vs base:* Broadwell (AVX2) Zen 4 (AVX-512) dim 1024 *+24%* −6% dim 8 *+36%* *+78%* Cause: f32::cosine_batch does the match *SIMD_SUPPORT + a #[target_feature] call *per vector*. On a wheel already built with target-cpu=haswell, that's pure overhead vs the pre-PR inlined f32x16/ f32x8 kernel. *Refinement:* gate the dispatch on #[cfg(target_feature = "avx2")] — AVX2-baseline builds use the inlined (byte-identical to pre-PR) kernels with no per-vector dispatch, and dispatch to AVX-512 *once per batch*, large dims only (a masked 512-bit load loses to a plain AVX2 load at 8 lanes). Sub-AVX2 builds keep your runtime path. *After (fix vs base):* Broadwell (AVX2) Zen 4 (AVX-512) dim 1024 +6% *−7%* dim 8 flat −3% Fast by default, AVX-512 still wins where it helps. Notes: the +6% at dim 1024 on AVX2 is a codegen-unit artifact (the kernel there is byte-identical to pre-PR), not the dispatch path. I only reworked f32 cosine — dot/l2/norm_l2 have the same per-vector shape and likely the same regression. Branch: https://github.com/stumpylog/lance/tree/cosine-batch-dispatch-fix — happy to PR it against your branch. (Downstream context: paperless-ngx/paperless-ngx#12970 <paperless-ngx/paperless-ngx#12970>.) — Reply to this email directly, view it on GitHub <#6630?email_source=notifications&email_token=ABKN6LEKEHRXNJUUKNCC2WD47G5AJA5CNFSNUABFM5UWIORPF5TWS5BNNB2WEL2JONZXKZKDN5WW2ZLOOQXTINRXGM4TKMRQGMZ2M4TFMFZW63VGMF2XI2DPOKSWK5TFNZ2KYZTPN52GK4S7MNWGSY3L#issuecomment-4673952033>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/ABKN6LDI2FDF6RKPOSM7AR347G5AJAVCNFSNUABFKJSXA33TNF2G64TZHM2TCMJWHEYTGOBQHNEXG43VMU5TIMZUGA2TQMBRHA4KC5QC> . Triage notifications, keep track of coding agent tasks and review pull requests on the go with GitHub Mobile for iOS <https://github.com/notifications/mobile/ios/ABKN6LBY7GQWJQTQAFWJUM347G5AJA5CNFSNUABFM5UWIORPF5TWS5BNNB2WEL2JONZXKZKDN5WW2ZLOOQXTINRXGM4TKMRQGMZ2M4TFMFZW63VGMF2XI2DPOKSWK5TFNZ2KUZTPN52GK4S7NFXXG> and Android <https://github.com/notifications/mobile/android/ABKN6LAYQNGZLTE6W6ENDGL47G5AJA5CNFSNUABFM5UWIORPF5TWS5BNNB2WEL2JONZXKZKDN5WW2ZLOOQXTINRXGM4TKMRQGMZ2M4TFMFZW63VGMF2XI2DPOKSWK5TFNZ2K4ZTPN52GK4S7MFXGI4TPNFSA>. Download it today! You are receiving this because you authored the thread.Message ID: ***@***.***>

[tobocop2]

@westonpace

Just a friendly bump now that there are other folks with similar needs. I'm wondering if you could nudge someone on this team our way. Thank you very much.