@@ -83,6 +83,7 @@ int acp_dsp_block_write(struct snd_sof_dev *sdev, enum snd_sof_fw_blk_type blk_t
8383 }
8484 dest = adata -> data_buf + offset ;
8585 adata -> fw_data_bin_size = size + offset ;
86+ adata -> is_dram_in_use = true;
8687 break ;
8788 case SOF_FW_BLK_TYPE_SRAM :
8889 offset = offset - desc -> sram_pte_offset ;
@@ -153,7 +154,7 @@ int acp_dsp_pre_fw_run(struct snd_sof_dev *sdev)
153154 struct pci_dev * pci = to_pci_dev (sdev -> dev );
154155 const struct sof_amd_acp_desc * desc = get_chip_info (sdev -> pdata );
155156 struct acp_dev_data * adata ;
156- unsigned int src_addr , size_fw ;
157+ unsigned int src_addr , size_fw , dest_addr ;
157158 u32 page_count , dma_size ;
158159 int ret ;
159160
@@ -174,20 +175,21 @@ int acp_dsp_pre_fw_run(struct snd_sof_dev *sdev)
174175 dev_err (sdev -> dev , "SHA DMA transfer failed status: %d\n" , ret );
175176 return ret ;
176177 }
177- configure_pte_for_fw_loading (FW_DATA_BIN , ACP_DRAM_PAGE_COUNT , adata );
178-
179- src_addr = ACP_SYSTEM_MEMORY_WINDOW + page_count * ACP_PAGE_SIZE ;
180- ret = configure_and_run_dma (adata , src_addr , ACP_DATA_RAM_BASE_ADDRESS ,
181- adata -> fw_data_bin_size );
182- if (ret < 0 ) {
183- dev_err (sdev -> dev , "acp dma configuration failed: %d\n" , ret );
184- return ret ;
178+ if (adata -> is_dram_in_use ) {
179+ configure_pte_for_fw_loading (FW_DATA_BIN , ACP_DRAM_PAGE_COUNT , adata );
180+ src_addr = ACP_SYSTEM_MEMORY_WINDOW + (page_count * ACP_PAGE_SIZE );
181+ dest_addr = ACP_DRAM_BASE_ADDRESS ;
182+
183+ ret = configure_and_run_dma (adata , src_addr , dest_addr , adata -> fw_data_bin_size );
184+ if (ret < 0 ) {
185+ dev_err (sdev -> dev , "acp dma configuration failed: %d\n" , ret );
186+ return ret ;
187+ }
188+ ret = acp_dma_status (adata , 0 );
189+ if (ret < 0 )
190+ dev_err (sdev -> dev , "acp dma transfer status: %d\n" , ret );
185191 }
186192
187- ret = acp_dma_status (adata , 0 );
188- if (ret < 0 )
189- dev_err (sdev -> dev , "acp dma transfer status: %d\n" , ret );
190-
191193 if (desc -> rev > 3 ) {
192194 /* Cache Window enable */
193195 snd_sof_dsp_write (sdev , ACP_DSP_BAR , ACP_DSP0_CACHE_OFFSET0 , desc -> sram_pte_offset );
@@ -197,10 +199,12 @@ int acp_dsp_pre_fw_run(struct snd_sof_dev *sdev)
197199 /* Free memory once DMA is complete */
198200 dma_size = (PAGE_ALIGN (sdev -> basefw .fw -> size ) >> PAGE_SHIFT ) * ACP_PAGE_SIZE ;
199201 dma_free_coherent (& pci -> dev , dma_size , adata -> bin_buf , adata -> sha_dma_addr );
200- dma_free_coherent (& pci -> dev , ACP_DEFAULT_DRAM_LENGTH , adata -> data_buf , adata -> dma_addr );
201202 adata -> bin_buf = NULL ;
202- adata -> data_buf = NULL ;
203-
203+ if (adata -> is_dram_in_use ) {
204+ dma_free_coherent (& pci -> dev , ACP_DEFAULT_DRAM_LENGTH , adata -> data_buf ,
205+ adata -> dma_addr );
206+ adata -> data_buf = NULL ;
207+ }
204208 return ret ;
205209}
206210EXPORT_SYMBOL_NS (acp_dsp_pre_fw_run , SND_SOC_SOF_AMD_COMMON );
0 commit comments