Event-Driven SNN Accelerator for FPGA

Energy-efficient, spike-triggered SNN accelerator on PYNQ-Z2 with a native Python/PyTorch-style software stack.

Current Status

• FPGA target: Zynq-7020 (PYNQ-Z2)
• Canonical PL clock: 80 MHz
• Maintained workflow: native library-first
• Supported scenarios:
  1. GPU training -> FPGA inference
  2. FPGA on-chip STDP train + inference

Quick Start

git clone https://github.com/metr0jw/Event-Driven-Spiking-Neural-Network-Accelerator-for-FPGA.git
cd Event-Driven-Spiking-Neural-Network-Accelerator-for-FPGA
./setup.sh

import numpy as np
from snn_fpga_accelerator import SNNAccelerator

accel = SNNAccelerator(simulation_mode=True)
output = accel.forward(np.array([[0, 0.0, 1.0]], dtype=np.float32))

Project Direction

This repository uses a native workflow built around snn_fpga_accelerator.

• Maintained path: native PyTorch-style training/export/runtime
• Removed from supported path: SpikingJelly auto-conversion

Features

• Fixed-point LIF neuron and event-router hardware
• On-chip STDP and R-STDP support
• Native Python/PyTorch-style API
• Host/runtime tooling for export, parity, and board execution
• RTL + HLS co-design for inference and learning

Public Documentation

• Developer Guide
• API Reference
• Architecture
• User Guide

Examples

python examples/pytorch/mnist_training_example.py
python examples/pytorch/r_stdp_learning_example.py
python examples/pytorch/mozafari_rstdp_faithful.py

Project Structure

hardware/
software/python/
examples/
docs/
scripts/
tests/

Citation

@misc{lee2025snnaccelerator,
  title={Event-Driven Spiking Neural Network Accelerator for FPGA},
  author={Lee, Jiwoon},
  year={2025},
  url={https://github.com/metr0jw/Event-Driven-Spiking-Neural-Network-Accelerator-for-FPGA}
}

License

MIT License - see LICENSE