CMOS-VLSI-Design-Cadence

CMOS logic and sequential circuit design with schematic, simulation, layout, DRC & LVS using Cadence Virtuoso.

🧠 CMOS VLSI Design using Cadence Virtuoso

This repository contains transistor-level CMOS circuit design, simulation, and physical layout verification performed using Cadence Virtuoso.

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🔄 Complete Design Flow Implemented

• Schematic Design
• DC Analysis (Voltage Transfer Characteristics)
• Transient Simulation
• Functional Verification
• Layout Design
• DRC (Design Rule Check)
• LVS (Layout vs Schematic Verification)

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📌 Circuits Designed

🔹 Combinational Logic

• CMOS Inverter
• 2-Input NAND Gate
• 2-Input NOR Gate
• XOR & XNOR
• Half Adder
• Full Adder
• 2:1 Multiplexer
• 4:1 Multiplexer

🔹 Sequential Logic

• D Flip-Flop
• SR Flip-Flop
• JK Flip-Flop

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🏗 Layout Verification

• DRC: ✅ Zero Errors
• LVS: ✅ Netlist Matched
• Physical layers used: N-well, Diffusion, Poly, Metal

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⚙ Tools Used

• Cadence Virtuoso (Schematic & Layout)
• ADE for DC & Transient Analysis

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🎯 Key Concepts Applied

• CMOS Pull-Up & Pull-Down Networks
• W/L Ratio Optimization
• Propagation Delay Analysis
• Switching Characteristics
• Sequential Timing Behavior
• Layout Parasitic Awareness

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📎 About This Project

This project demonstrates complete front-end and back-end CMOS design flow used in digital VLSI systems and semiconductor design environments.

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👨‍💻 Author: Shashikant

CMOS Inverter