Pinned Loading

1. hdl-mul hdl-mul Public

   The RTL implementation of a 8-bit pipelined signed integer multiplication module with some optimization techniques and testbench.

   SystemVerilog 1

2. adapter_verif adapter_verif Public

   Формальная и функциональная верификация переходника с интерфейса valid-ready на интерфейс valid-credit.

   SystemVerilog

3. systemverilog-homework-solutions systemverilog-homework-solutions Public

   Forked from chipdesignschool/systemverilog-homework

   Solutions of SystemVerilog exercises

   SystemVerilog

4. current_sensor current_sensor Public

   Прошивка микроконтроллера ATMega328P для датчика тока Холла.

   C