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Support for Cadence Xcelium simulator #193

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f16ab13
Support for Cadence Xcelium simulator
uge Mar 20, 2025
575893b
Rename 'xm' to 'xcelium'
uge Mar 31, 2025
6634659
Fix another xm->xcelium
uge Mar 31, 2025
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2 changes: 2 additions & 0 deletions README.md
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Original file line number Diff line number Diff line change
Expand Up @@ -290,6 +290,7 @@ Individual commands may also set tool-specific targets:

- `vsim`
- `vcs`
- `xm`
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- `verilator`
- `synopsys`
- `riviera`
Expand Down Expand Up @@ -421,6 +422,7 @@ Supported formats:
- `flist-plus`: A flat file list amenable to be directly inlined into the invocation command of a tool, e.g. `verilate $(bender script flist)`.
- `vsim`: A Tcl compilation script for Mentor ModelSim/QuestaSim.
- `vcs`: A Tcl compilation script for VCS.
- `xm`: A Tcl compilation script for Cadence Xcelium.
- `verilator`: Command line arguments for Verilator.
- `synopsys`: A Tcl compilation script for Synopsys DC and DE.
- `formality`: A Tcl compilation script for Formality (as reference design).
Expand Down
14 changes: 12 additions & 2 deletions src/cmd/script.rs
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Expand Up @@ -48,6 +48,7 @@ pub fn new() -> Command {
PossibleValue::new("flist-plus"),
PossibleValue::new("vsim"),
PossibleValue::new("vcs"),
PossibleValue::new("xm"),
PossibleValue::new("verilator"),
PossibleValue::new("synopsys"),
PossibleValue::new("formality"),
Expand Down Expand Up @@ -87,7 +88,7 @@ pub fn new() -> Command {
.arg(
Arg::new("vlog-arg")
.long("vlog-arg")
.help("Pass an argument to vlog calls (vsim/vlogan/riviera only)")
.help("Pass an argument to vlog calls (vsim/xm/vlogan/riviera only)")
.num_args(1..)
.action(ArgAction::Append)
.value_parser(value_parser!(String)),
Expand Down Expand Up @@ -219,6 +220,7 @@ pub fn run(sess: &Session, matches: &ArgMatches) -> Result<()> {
"flist-plus" => vec!["flist"],
"vsim" => vec!["vsim", "simulation"],
"vcs" => vec!["vcs", "simulation"],
"xm" => vec!["xm", "simulation"],
"verilator" => vec!["verilator", "synthesis"],
"synopsys" => vec!["synopsys", "synthesis"],
"formality" => vec!["synopsys", "synthesis", "formality"],
Expand Down Expand Up @@ -299,12 +301,13 @@ pub fn run(sess: &Session, matches: &ArgMatches) -> Result<()> {
if (matches.contains_id("vcom-arg") || matches.contains_id("vlog-arg"))
&& format != "vsim"
&& format != "vcs"
&& format != "xm"
&& format != "riviera"
&& format != "template"
&& format != "template_json"
{
return Err(Error::new(
"vsim/vcs-only options can only be used for 'vcs', 'vsim' or 'riviera' format!",
"vsim/vcs-only options can only be used for 'vcs', 'xm', 'vsim' or 'riviera' format!",
));
}
if (matches.get_flag("only-defines")
Expand Down Expand Up @@ -350,6 +353,13 @@ pub fn run(sess: &Session, matches: &ArgMatches) -> Result<()> {
targets,
srcs,
),
"xm" => emit_template(
sess,
include_str!("../script_fmt/xm_sh.tera"),
matches,
targets,
srcs,
),
"verilator" => emit_template(
sess,
include_str!("../script_fmt/verilator_sh.tera"),
Expand Down
16 changes: 16 additions & 0 deletions src/script_fmt/xm_sh.tera
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@@ -0,0 +1,16 @@
#!/usr/bin/env bash
# {{ HEADER_AUTOGEN }}
{% if abort_on_error %}# Set propagation of error to exit on first error
set -e
{% endif %}
ROOT="{{ root }}"
{% for group in srcs %}
{% if group.file_type == 'verilog' %}xmvlog -sv \
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@micprog micprog Mar 31, 2025

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I see you have support for verilog files, which is a great start. As bender is generally built to support vhdl files as well, and this simulator supports vhdl, it would be great to ensure compatibility here as well.

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@uge uge Mar 31, 2025

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We don't have any VHDL code internally to test with. If there is a public Bender repo with VHDL code and a simulation target, please refer me to it an I'll try to include the template.

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@yvantor yvantor Oct 5, 2025 •
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Hi @uge, we have a can_bus entirely written in VHDL. You can also find it integrated in Cheshire if you need an example with both Verilog and VHDL IPs.

{% for tmp_arg in vlog_args %}{{ tmp_arg }} \
{% endfor %}{% for define in group.defines %}"+define+{{ define.0 | upper }}{% if define.1 %}={{ define.1 }}{% endif %}" \
{% endfor %}{% for incdir in group.incdirs %}"+incdir+{{ incdir | replace(from=root, to='$ROOT') }}" \
{% endfor %} \
{% for file in group.files %}"{{ file | replace(from=root, to='$ROOT') }}" {% if not loop.last %}\
{% endif %}{% endfor %}
{% endif %}
{% endfor %}