CAMSS: CPHY Support for RB3G2, RB4, RB8 - #872
Conversation
The lane mask must be multiplied by 2, but this was accidentally omitted. Link: https://lore.kernel.org/r/20260617-qcom-cphy-v9-1-83da8a8e4e44@ixit.cz Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Suggested-by: Nihal Kumar Gupta <nihal.gupta@oss.qualcomm.com> Signed-off-by: David Heidelberg <david@ixit.cz> Signed-off-by: Anusha Arun Nandi <anusha.nandi@oss.qualcomm.com>
Read PHY configuration from the device-tree bus-type and save it into the csiphy structure for later use. For C-PHY, skip clock line configuration, as there is none. Link: https://lore.kernel.org/r/20260617-qcom-cphy-v9-2-83da8a8e4e44@ixit.cz Acked-by: Cory Keitz <ckeitz@amazon.com> Reviewed-by: Bryan O'Donoghue <bod@kernel.org> Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: David Heidelberg <david@ixit.cz> Signed-off-by: Anusha Arun Nandi <anusha.nandi@oss.qualcomm.com>
…g C-PHY lanes So far, only D-PHY mode was supported, which uses even bits when enabling or masking lanes. For C-PHY configuration, the hardware instead requires using the odd bits. Since there can be unrecognized configuration allow returning failure. Link: https://lore.kernel.org/r/20260617-qcom-cphy-v9-3-83da8a8e4e44@ixit.cz Acked-by: Cory Keitz <ckeitz@amazon.com> Reviewed-by: Bryan O'Donoghue <bod@kernel.org> Signed-off-by: David Heidelberg <david@ixit.cz> Signed-off-by: Anusha Arun Nandi <anusha.nandi@oss.qualcomm.com>
Inherit C-PHY information from CSIPHY, so we can configure CSID properly. CSI2_RX_CFG0_PHY_TYPE_SEL must be set to 1, when C-PHY mode is used. Link: https://lore.kernel.org/r/20260617-qcom-cphy-v9-4-83da8a8e4e44@ixit.cz Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Acked-by: Cory Keitz <ckeitz@amazon.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: David Heidelberg <david@ixit.cz> Signed-off-by: Anusha Arun Nandi <anusha.nandi@oss.qualcomm.com>
…on is available The lanes must not be initialized before the driver has access to the lane configuration, as it depends on whether D-PHY or C-PHY mode is in use. Move the lane initialization to csiphy_lanes_enable which is called when the configuration structures are available. Link: https://lore.kernel.org/r/20260617-qcom-cphy-v9-5-83da8a8e4e44@ixit.cz Co-developed-by: Petr Hodina <phodina@protonmail.com> Signed-off-by: Petr Hodina <phodina@protonmail.com> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Acked-by: Cory Keitz <ckeitz@amazon.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: David Heidelberg <david@ixit.cz> Signed-off-by: Anusha Arun Nandi <anusha.nandi@oss.qualcomm.com>
…PHY init Add a PHY configuration sequence for the sdm845 which uses a Qualcomm Gen 2 version 1.1 CSI-2 PHY. The PHY can be configured as two phase or three phase in C-PHY or D-PHY mode. This configuration supports three-phase C-PHY mode. Link: https://lore.kernel.org/r/20260617-qcom-cphy-v9-6-83da8a8e4e44@ixit.cz Acked-by: Cory Keitz <ckeitz@amazon.com> Signed-off-by: David Heidelberg <david@ixit.cz> Signed-off-by: Anusha Arun Nandi <anusha.nandi@oss.qualcomm.com>
… C-PHY init These values should improve C-PHY behaviour. Should match most recent Qualcomm code. Link: https://lore.kernel.org/r/20260617-qcom-cphy-v9-7-83da8a8e4e44@ixit.cz Acked-by: Cory Keitz <ckeitz@amazon.com> Suggested-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: David Heidelberg <david@ixit.cz> Signed-off-by: Anusha Arun Nandi <anusha.nandi@oss.qualcomm.com>
… frequency Ensure that the link frequency divider correctly accounts for C-PHY operation. The divider differs between D-PHY and C-PHY, as described in the MIPI CSI-2 specification. For more details, see: https://docs.kernel.org/driver-api/media/tx-rx.html#pixel-rate Link: https://lore.kernel.org/r/20260617-qcom-cphy-v9-8-83da8a8e4e44@ixit.cz Suggested-by: Sakari Ailus <sakari.ailus@linux.intel.com> Link: https://docs.kernel.org/driver-api/media/tx-rx.html#pixel-rate Signed-off-by: David Heidelberg <david@ixit.cz> Signed-off-by: Anusha Arun Nandi <anusha.nandi@oss.qualcomm.com>
After all the changes done we can now safely enable C-PHY for a SoC where it's available. Link: https://lore.kernel.org/r/20260617-qcom-cphy-v9-9-83da8a8e4e44@ixit.cz Acked-by: Cory Keitz <ckeitz@amazon.com> Reviewed-by: Bryan O'Donoghue <bod@kernel.org> Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: David Heidelberg <david@ixit.cz> Signed-off-by: Anusha Arun Nandi <anusha.nandi@oss.qualcomm.com>
Program the CSIPHY common-control registers during lane enable so SA8775P uses the required 3-phase 1.5 Gsps reset-release values for both C-PHY and D-PHY. Keep the existing reset-release value for the other CAMSS variants. Link: https://lore.kernel.org/r/20260717231331.1229693-2-anusha.nandi@oss.qualcomm.com Co-developed-by: Anusha Arun Nandi <anusha.nandi@oss.qualcomm.com> Signed-off-by: Anusha Arun Nandi <anusha.nandi@oss.qualcomm.com> Signed-off-by: Jigarkumar Zala <jigarkumar.zala@oss.qualcomm.com>
Program the gen3 CSID CSI2 RX PHY type field from the configured PHY type. The RX path needs this value to distinguish C-PHY from D-PHY input, so leaving it at the default makes C-PHY configuration incomplete. Link: https://lore.kernel.org/r/20260717231331.1229693-3-anusha.nandi@oss.qualcomm.com Co-developed-by: Anusha Arun Nandi <anusha.nandi@oss.qualcomm.com> Signed-off-by: Anusha Arun Nandi <anusha.nandi@oss.qualcomm.com> Signed-off-by: Jigarkumar Zala <jigarkumar.zala@oss.qualcomm.com>
Add the lane_regs_sa8775p_3ph[] register table for the sa8775p Gen3 CSIPHY at 1.5 Gsps, and select it in csiphy_lanes_enable() for CAMSS_8775P when the endpoint is configured for C-PHY, falling back to the existing sa8775p D-PHY table otherwise. Link: https://lore.kernel.org/r/20260717231331.1229693-4-anusha.nandi@oss.qualcomm.com Co-developed-by: Anusha Arun Nandi <anusha.nandi@oss.qualcomm.com> Signed-off-by: Anusha Arun Nandi <anusha.nandi@oss.qualcomm.com> Signed-off-by: Jigarkumar Zala <jigarkumar.zala@oss.qualcomm.com>
Share the C-PHY/D-PHY lane_regs selection for CAMSS_8300 so the sa8300 platform uses the same 3ph handling as CAMSS_8775P. Also drop CAMSS_8300 from the missing-C-PHY-table guard now that a C-PHY table is provided. Link: https://lore.kernel.org/r/20260717231331.1229693-5-anusha.nandi@oss.qualcomm.com Co-developed-by: Jigarkumar Zala <jigarkumar.zala@oss.qualcomm.com> Signed-off-by: Jigarkumar Zala <jigarkumar.zala@oss.qualcomm.com> Signed-off-by: Anusha Arun Nandi <anusha.nandi@oss.qualcomm.com>
…er settings The C-PHY PHY register configuration needs to vary with the link (symbol) data rate. Until now only a single base lane_regs table was applied per platform, regardless of the negotiated rate. Introduce a data-rate selection mechanism for C-PHY: - Add struct data_rate_reg_info describing a per-bandwidth register override table. - Add csiphy_cphy_data_rate_config(), which selects the first table entry whose bandwidth satisfies the required PHY data rate (derived from the resolved link frequency) and writes those overrides on top of the base lane_regs configuration. The settle-count parameter types are handled specially. When the link frequency cannot be resolved, it falls back to the lowest supported rate. - Add per-data-rate register tables and data_rate_settings tables for sa8775p and 8300(1.5/1.7/2.5/3.5/4.5 GSpS) and sm8250 (2.5/3.5/4.5 GSpS). - Select the appropriate data-rate settings table in csiphy_lanes_enable() for both platforms when the endpoint is configured for C-PHY. Link: https://lore.kernel.org/r/20260717231331.1229693-6-anusha.nandi@oss.qualcomm.com Co-developed-by: Jigarkumar Zala <jigarkumar.zala@oss.qualcomm.com> Signed-off-by: Jigarkumar Zala <jigarkumar.zala@oss.qualcomm.com> Signed-off-by: Anusha Arun Nandi <anusha.nandi@oss.qualcomm.com>
A link is invalid if the local CSIPHY endpoint and the remote sensor endpoint describe different bus types. Such a mismatch can otherwise go undetected until later probe or streaming failures. Parse the remote endpoint in camss_parse_endpoint_node() and compare its bus-type with the local endpoint. Reject the link with -EINVAL if the two ends disagree, so C-PHY/D-PHY mismatches are caught early during probe. Link: https://lore.kernel.org/r/20260717231331.1229693-7-anusha.nandi@oss.qualcomm.com Co-developed-by: Jigarkumar Zala <jigarkumar.zala@oss.qualcomm.com> Signed-off-by: Jigarkumar Zala <jigarkumar.zala@oss.qualcomm.com> Signed-off-by: Anusha Arun Nandi <anusha.nandi@oss.qualcomm.com>
PR #872 — validate-patchPR: #872
Final Summary
|
PR #872 — checker-log-analyzerPR: #872
Detailed report: Full report
|
Test Matrix
|
Test jobs on de05558 |
|
Shiraz Hashim (@shashim-quic) I see there is a NAK from community on below series : aarunnan are these comments addressed ? |
Yes, the comments are addressed and its come to a conclusion there will be another patchset version. |
Enablement of CPHY for RB3G2, RB4, RB8.
CRs-Fixed: 4617368