test: smoke-test the pre-merge build check - #61
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Bjordis Collaku (bjordiscollaku) wants to merge 1308 commits into
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test: smoke-test the pre-merge build check#61Bjordis Collaku (bjordiscollaku) wants to merge 1308 commits into
Bjordis Collaku (bjordiscollaku) wants to merge 1308 commits into
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Add CAMSS driver support for Shikra SoC. Add high level resource definitions for 2 CSIPHY, 2 CSID and 2 VFE instances along with the interconnect bandwidth votes for AHB, HF and SF MNOC paths. Co-developed-by: Vikram Sharma <vikramsa@qti.qualcomm.com> Signed-off-by: Vikram Sharma <vikramsa@qti.qualcomm.com> Signed-off-by: Prashant Shrotriya <pshrotri@qti.qualcomm.com> (cherry picked from commit 45fa97cf9097a8a17e7ada36e3d6b0ef61abc856)
SMEM_SMSM_SIZE_INFO (id 419) is not populated by the boot firmware on Shikra. The SMSM driver falls back to SMSM_DEFAULT_NUM_HOSTS when this segment is absent, which causes SMEM_SMSM_CPU_INTR_MASK (id 333) to be allocated with the wrong size. The upstream default of 3 allocates 8*3*4 = 96 bytes. Shikra modem firmware expects 8*5*4 = 160 bytes, matching the num_hosts=5 used by the downstream kernel. The size mismatch causes the modem to crash on boot with "smsm.c: Bad pointer from smem_alloc". Increasing the host count only results in a larger allocation, so this change is safe for existing platforms. Increase the default to 5 to match the modem firmware expectation. Signed-off-by: Vishnu Santhosh <vishnu.santhosh@oss.qualcomm.com> (cherry picked from commit d2a3f3aea2006f4275c395debf869dc3c22d97df)
The driver hardcodes IRQF_TRIGGER_HIGH when registering the BAM interrupt, which overrides the trigger type specified in the device tree. This is incorrect for platforms like Shikra where the A2 BAM requires edge-triggered interrupts. Use IRQF_TRIGGER_NONE instead, which causes the kernel to use the trigger type already configured by platform_get_irq() when it parsed the device tree interrupts property. This makes the driver platform-agnostic. Signed-off-by: Vishnu Santhosh <vishnu.santhosh@oss.qualcomm.com> (cherry picked from commit 410819e845aef56a5894820480621e075062660d)
This driver provides access to modem data channels on platforms using the A2 BAM hardware, including Shikra. Signed-off-by: Vishnu Santhosh <vishnu.santhosh@oss.qualcomm.com> (cherry picked from commit 072917fece4c997a5b03f49e7c1a985ef7ba0250)
Add support for the Adreno A704 GPU (chip ID 0x07000400). It belongs to the A610 family and shares its configuration with the A702, including HWCG, UBWC settings, and CP memory pool size. Introduce adreno_is_a704() and include A704 in adreno_is_a610_family(). Signed-off-by: Aditya Sherawat <asherawa@qti.qualcomm.com> (cherry picked from commit 0084527ac646fd6ed0dbd287e07b6f631f7b7e14)
The Shikra SoC uses an Adreno A704 GPU identified by chip ID 0x07000400. Signed-off-by: Aditya Sherawat <asherawa@qti.qualcomm.com> (cherry picked from commit 95d1d482a0fa8eda19bd7ca4e89263dc3eedebc7)
Drop generic compatible approach, and add Shikra specific bindings. Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com> (cherry picked from commit 1307dc19fc1eb6ad76e4b37e1ada0d3c0a6b392e)
Update the compatible string to "qcom,shikra-epss" as per the latest bindings. Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com> (cherry picked from commit 91c68036633225518db862ad3d717edb0f18f6ad)
Add ftrace tracepoints to SMSM for observability of state bit updates, IPC kicks, interrupt handling, and IRQ mask/unmask operations. Introduce a trace header and wire CFLAGS_smsm.o so the trace header is found via -I$(src). Signed-off-by: Vishnu Santhosh <vishnu.santhosh@oss.qualcomm.com> (cherry picked from commit 4fc7567e7a80c93a5cbf72ba3b9d5e02525ecd22)
Add ftrace tracepoints to the BAM-DMUX driver for observability of channel open/close (local and remote), RX callbacks, power on/off transitions, power control IRQs, and each step of the runtime resume sequence. Introduce a trace header and wire CFLAGS_qcom_bam_dmux.o so the trace header is found via -I$(src). Signed-off-by: Vishnu Santhosh <vishnu.santhosh@oss.qualcomm.com> (cherry picked from commit a34947dc1449769d07054e56f386687fef5540b0)
This patch introduces the creation of AEST platform devices, where each device represents a logical "error node device" grouping one or more AEST nodes from the ACPI table. Instead of relying on the optional 'error_node_device' field in the AEST table[1], this commit uses the interrupt number as the sole identifier for the parent device. This design simplifies the driver logic by providing a single, consistent mechanism for grouping nodes. The 'error_node_device' field can be unspecified, but an AEST node is always physically associated with a parent component. The interrupt number serves as a reliable proxy for this association. This approach is based on the safe assumption that distinct hardware components (e.g., SMMU, CMN, GIC) are assigned unique error interrupts and do not share them. [1]: https://developer.arm.com/documentation/den0085/latest Signed-off-by: Ruidong Tian <tianruidong@linux.alibaba.com> Link: https://patch.msgid.link/20260122094656.73399-2-tianruidong@linux.alibaba.com Signed-off-by: Umang Chheda <umang.chheda@oss.qualcomm.com> (cherry picked from commit c1d94cc19c0c63d78ffc8dd0cdfd35f12790ccde)
Parse register information from the AEST table in the probe function, create corresponding structures, and mappings AEST record. Signed-off-by: Ruidong Tian <tianruidong@linux.alibaba.com> Link: https://patch.msgid.link/20260122094656.73399-3-tianruidong@linux.alibaba.com Signed-off-by: Umang Chheda <umang.chheda@oss.qualcomm.com> (cherry picked from commit 7530c56275309565d43b56a1db6fb6df4326fab8)
Support for various AEST group formats allows for flexible configuration of AEST node address space sizes and maximum record counts per group. Signed-off-by: Ruidong Tian <tianruidong@linux.alibaba.com> Link: https://patch.msgid.link/20260122094656.73399-4-tianruidong@linux.alibaba.com Signed-off-by: Umang Chheda <umang.chheda@oss.qualcomm.com> (cherry picked from commit 7da73d25db320395408f576490f3dc1018124eda)
…IO register Use record_read/write to simultaneously read and write system registers and MMIO registers while maintaining code conciseness. Signed-off-by: Ruidong Tian <tianruidong@linux.alibaba.com> Link: https://patch.msgid.link/20260122094656.73399-5-tianruidong@linux.alibaba.com Signed-off-by: Umang Chheda <umang.chheda@oss.qualcomm.com> (cherry picked from commit 0a2c44115f9a2e9f86f3f5684ad71e1b4206872c)
The RAS version of a component can be probed via its ERRDEVARCH register. In cases where a component (e.g., SMMU) does not implement an ERRDEVARCH register, the driver falls back to using the RAS version of the Processing Element (PE). Signed-off-by: Ruidong Tian <tianruidong@linux.alibaba.com> Link: https://patch.msgid.link/20260122094656.73399-6-tianruidong@linux.alibaba.com Signed-off-by: Umang Chheda <umang.chheda@oss.qualcomm.com> (cherry picked from commit 53f61f152922baf7cab5f563c80bd2cba7fa88a5)
Add inject register descripted in Common Fault Injection Model Extension. Signed-off-by: Ruidong Tian <tianruidong@linux.alibaba.com> Link: https://patch.msgid.link/20260122094656.73399-7-tianruidong@linux.alibaba.com Signed-off-by: Umang Chheda <umang.chheda@oss.qualcomm.com> (cherry picked from commit 4425653637bbf9c36ece49d1bc2e10f3fff18646)
The CE threshold defines the number of Correctable Errors (CE) that must occur in a record before triggering an interrupt. Error records support multiple threshold configurations, including 8B, 16B, and 32B. This patch detects the supported threshold settings for error records and sets the default threshold to 1, ensuring an interrupt is generated for every CE occurrence. Signed-off-by: Ruidong Tian <tianruidong@linux.alibaba.com> Link: https://patch.msgid.link/20260122094656.73399-8-tianruidong@linux.alibaba.com Signed-off-by: Umang Chheda <umang.chheda@oss.qualcomm.com> (cherry picked from commit 8dcb893bc634dce1c38a0401c0159867de5aac24)
The interrupt numbers for certain error records may be explicitly programmed into their configuration register. And for PPIs, each core will maintains its own copy of the aest_device structure. Given that handling RAS errors entails complex processes such as EDAC and memory_failure, all handling is deferred to and handled within a bottom-half context. Signed-off-by: Ruidong Tian <tianruidong@linux.alibaba.com> Link: https://patch.msgid.link/20260122094656.73399-9-tianruidong@linux.alibaba.com Signed-off-by: Umang Chheda <umang.chheda@oss.qualcomm.com> (cherry picked from commit 73c5b35a2d45dceccfe6adcebe06076288f33296)
Move the configuration of interrupts and CE thresholds into the CPU hotplug callbacks for the per-CPU AEST node. Signed-off-by: Ruidong Tian <tianruidong@linux.alibaba.com> Link: https://patch.msgid.link/20260122094656.73399-10-tianruidong@linux.alibaba.com Signed-off-by: Umang Chheda <umang.chheda@oss.qualcomm.com> (cherry picked from commit 70005f68542182afc4fd2e863b30b0f6a23cfcf9)
Exposes certain AEST driver information to userspace.
Only ROOT can access these interface because it includes
hardware-sensitive information:
ls /sys/kernel/debug/aest/
memory<id> smmu<id> ...
ls /sys/kernel/debug/aest/memory<id>/
record0 record1 ...
All details at:
Documentation/ABI/testing/debugfs-aest
Signed-off-by: Ruidong Tian <tianruidong@linux.alibaba.com>
Link: https://patch.msgid.link/20260122094656.73399-11-tianruidong@linux.alibaba.com
Signed-off-by: Umang Chheda <umang.chheda@oss.qualcomm.com>
(cherry picked from commit 166ac6de5503aa748a50da36151cdf2a6b9c84f5)
This commit introduces error counting functionality for AEST records. Previously, error statistics were not directly available for individual error records or AEST nodes. Signed-off-by: Ruidong Tian <tianruidong@linux.alibaba.com> Link: https://patch.msgid.link/20260122094656.73399-12-tianruidong@linux.alibaba.com Signed-off-by: Umang Chheda <umang.chheda@oss.qualcomm.com> (cherry picked from commit 4b546221d48c26f969eb3b0a800188a9437144a0)
This commit introduces the ability to configure the Corrected Error (CE) threshold for AEST records through debugfs. This allows administrators to dynamically adjust the CE threshold for error reporting. Signed-off-by: Ruidong Tian <tianruidong@linux.alibaba.com> Link: https://patch.msgid.link/20260122094656.73399-13-tianruidong@linux.alibaba.com Signed-off-by: Umang Chheda <umang.chheda@oss.qualcomm.com> (cherry picked from commit cfc3c506c40440be6ba9ce856c7b921c13ff6ab4)
AEST offers both soft and hard injection. Soft injection simulates errors in software, providing flexibility to define the error register content. Hard injection, on the other hand, utilizes error injection registers to introduce hardware faults, strictly requiring values that adhere to their specifications. Read Documentation/ABI/testing/debugfs-aest to learn how to use them. Signed-off-by: Ruidong Tian <tianruidong@linux.alibaba.com> Link: https://patch.msgid.link/20260122094656.73399-14-tianruidong@linux.alibaba.com Signed-off-by: Umang Chheda <umang.chheda@oss.qualcomm.com> (cherry picked from commit 4ab219a0f0530d127346d405dadd81243ea677a7)
AEST table include vendor error node to support the component that do not implement standard Arm RAS architecture[1]. Each vendor node may have their own initialize and interrupt handle function. This patch supply a framework to process vendor error nodes, the vendor process function is binded with vendor HID. [1]: https://developer.arm.com/documentation/ddi0587/latest/ Signed-off-by: Ruidong Tian <tianruidong@linux.alibaba.com> Link: https://patch.msgid.link/20260122094656.73399-15-tianruidong@linux.alibaba.com Signed-off-by: Umang Chheda <umang.chheda@oss.qualcomm.com> (cherry picked from commit 7eafc168926815372d64f3db10a650b6c80f3d9c)
The CMN (Coherent Mesh Network) architecture incorporates five distinct device types. Each device type is associated with an error group register set. The struct aest_cmn_700 models a single CMN instance, while struct aest_cmn_700_child represents an individual CMN device. CMN's error records utilize a memory-mapped single error record view [1]. Critically, one error record corresponds to one AEST node, implying that a single CMN instance can generate hundreds of AEST nodes. To manage this scale, this driver introduces a virtual AEST node, which represents an entire CMN device, such as an HNI or HNF. This allows an HNF AEST node, for instance, to leverage its errgsr register to pinpoint which specific error record has reported an error. During the AEST probe phase, the CMN AEST driver identifies the CMN node type using the cmn_node_info register. It then reorganizes all AEST nodes belonging to the same CMN node type into a cohesive CMN AEST node structure. To locate the relevant CMN register addresses, the CMN's presence in the DSDT is required, along with the CMN node offset specified in the AEST vendor specification data [1]. [1]: https://developer.arm.com/documentation/102308/latest/ Signed-off-by: Ruidong Tian <tianruidong@linux.alibaba.com> Link: https://patch.msgid.link/20260122094656.73399-16-tianruidong@linux.alibaba.com Signed-off-by: Umang Chheda <umang.chheda@oss.qualcomm.com> (cherry picked from commit f8822df5d85db1ae913455e3fba25b4e28402672)
Add a trace event for hardware errors reported by the ARMv8 RAS extension registers. userspace app can monitor this trace event and decode error information. Signed-off-by: Ruidong Tian <tianruidong@linux.alibaba.com> Link: https://patch.msgid.link/20260122094656.73399-17-tianruidong@linux.alibaba.com Signed-off-by: Umang Chheda <umang.chheda@oss.qualcomm.com> (cherry picked from commit b5a45a89ed06f88be6554ab937a93a5ccea2a2ec)
… messages Two related fixes for processor nodes with ACPI_AEST_PROC_FLAG_SHARED or ACPI_AEST_PROC_FLAG_GLOBAL set (e.g. cluster L3 cache, DSU): 1. aest_dev_is_oncore() returns true for any PROCESSOR_ERROR_NODE, causing shared processor nodes (which use an SPI) to take the cpuhp/PPI path. cpuhp_setup_state() is called instead of aest_online_dev(), so aest_config_irq() is never called and the hardware IRQ-config register is never programmed. Fix aest_dev_is_oncore() to check irq_is_percpu() on the registered IRQ. Only nodes whose FHI or ERI is a per-CPU PPI take the oncore path, nodes with an SPI take aest_online_dev(). 2. alloc_aest_node_name() uses processor_id for the node name of all processor nodes. Shared/global nodes have processor_id=0 (the field is unused when SHARED/GLOBAL is set), so every shared node and the per-PE node for CPU 0 both got the name "processor.0", making error logs ambiguous. For shared/global nodes, build the name as "processor.<resource_type>.<device_id>" (e.g. "processor.cache.1") so each node has a unique, meaningful identifier. Per-PE nodes keep the original "processor.<mpidr>" form. Also add proc_flags to struct aest_event so aest_print() can distinguish shared from per-PE nodes and print an appropriate message. Link: https://lore.kernel.org/lkml/20260505-aest-devicetree-support-v1-1-d5d6ffacf0a5@oss.qualcomm.com/ Signed-off-by: Umang Chheda <umang.chheda@oss.qualcomm.com> (cherry picked from commit 3a8e45a9473d4fe10deb0aed6dcddd5459364d93)
The error counts visible under: /sys/kernel/debug/aest/<dev>/processor<cpu>/<node>/err_count always reported zero, even though corrected errors (CEs) were being serviced by the interrupt handler. aest_oncore_dev_init_debugfs() sets up per CPU debugfs entries but wired them up incorrectly in two places: - this_cpu_ptr(adev->adev_oncore) was used inside for_each_possible_cpu(). This always selects the slot for the CPU executing the init code, so all debugfs files ended up referencing the same per CPU aest_device instance instead of the CPU indicated by the loop variable. - The code referenced adev->nodes[i], i.e. the template nodes allocated before __setup_ppi, rather than the per-CPU copies at percpu_dev->nodes[i]. The IRQ handler updates CE counters in the per-CPU records created by __setup_ppi, the template records are never touched at runtime, so err_count always read as zero. Fix this by: - Using per_cpu_ptr(adev->adev_oncore, cpu) when iterating over CPUs. Wiring debugfs files to percpu_dev->nodes[i] so counters reflect the data updated by the IRQ handler. - Using adev->nodes[i].name for debugfs directory names. The per-CPU node receives name via a shallow memcpy and is not the authoritative source. Link: https://lore.kernel.org/lkml/20260505-aest-devicetree-support-v1-2-d5d6ffacf0a5@oss.qualcomm.com/ Signed-off-by: Umang Chheda <umang.chheda@oss.qualcomm.com> (cherry picked from commit 8e82ad6656396ea34341195d9cc0760864eb9884)
The record_implemented bitmap uses the same semantics as the rest of the driver: a SET bit means the record is NOT implemented (skip it), a CLEAR bit means the record IS implemented (process it). aest_node_init_debugfs() and aest_node_err_count_show() were iterating all record_count records unconditionally, creating debugfs entries and accumulating error counts for unimplemented records too. Fix both functions to skip records where the corresponding bit is set in node->record_implemented, consistent with how aest_node_foreach_record() handles the same bitmap. Link: https://lore.kernel.org/lkml/20260505-aest-devicetree-support-v1-3-d5d6ffacf0a5@oss.qualcomm.com/ Signed-off-by: Umang Chheda <umang.chheda@oss.qualcomm.com> (cherry picked from commit 66ff7ded0f7e818f5b39d4f2b680ec41d2f3c658)
The driver unconditionally calls panic() whenever an unrecoverable, uncontainable UE (UET_UC or UET_UEU) is detected. There is no way for the user to suppress this behaviour, which makes it difficult to test UE injection or to run in environments where a kernel panic on every UE is undesirable. Add a module parameter `aest_panic_on_ue` When set to 0 the driver logs the UE and continues instead of panicking. Usage: # Boot time (kernel cmdline) aest.aest_panic_on_ue=0 # Runtime echo 0 > /sys/module/aest/parameters/aest_panic_on_ue Link: https://lore.kernel.org/lkml/20260505-aest-devicetree-support-v1-4-d5d6ffacf0a5@oss.qualcomm.com/ Signed-off-by: Umang Chheda <umang.chheda@oss.qualcomm.com> (cherry picked from commit 8c588f197bbc45769b100c1ce9bc739b379774c8)
Document the compatible string for inline crypto engine found on the Qualcomm X1E80100 SoC, used by the Hamoa IoT EVK board. Link: https://lore.kernel.org/all/20260722-devtool-v2-1-03f6c82d84fe@oss.qualcomm.com/ Signed-off-by: Wenjia Zhang <wenjz@qti.qualcomm.com> Signed-off-by: Abhinaba Rakshit <abhinaba.rakshit@oss.qualcomm.com>
Add the Inline Crypto Engine (ICE) device node to describe the hardware-accelerated inline encryption for UFS storage on the Hamoa IoT EVK board (Qualcomm X1E80100 SoC). Link: https://lore.kernel.org/all/20260722-devtool-v2-2-03f6c82d84fe@oss.qualcomm.com/ Signed-off-by: Wenjia Zhang <wenjz@qti.qualcomm.com> Signed-off-by: Abhinaba Rakshit <abhinaba.rakshit@oss.qualcomm.com>
…devices Add label properties to TPDM and CTI nodes in the hamoa device tree to provide human-readable identifiers for each CoreSight device. These labels allow userspace tools and the CoreSight framework to identify devices by name rather than by base address. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260414-add-label-to-coresight-device-v2-7-5017d07358f2@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Install Qualcomm camx DTBO overlay files by adding them to the dtb-$(CONFIG_ARCH_QCOM) build/install list. This makes DTBOs available through the standard dtbs_install flow and ensures they are included in distro kernel packages. Signed-off-by: Chandan Kumar Jha <cjha@qti.qualcomm.com>
…port The purwa-evk DTS currently lacks DAI links for DP0 and DP1, preventing the sound card from exposing these playback paths. Add the missing links to enable audio output on both DP interfaces. Link: https://lore.kernel.org/all/20260701063003.3082899-1-le.qi@oss.qualcomm.com/ Signed-off-by: Le Qi <le.qi@oss.qualcomm.com>
QCLINUX: arm64: dts: qcom: Install camx DTBO overlays
FROMLIST: Enable ICE for UFS on Hamoa IoT EVK
BACKPORT: arm64: dts: qcom: hamoa: Add label properties to CoreSight devices
FROMLIST: arm64: dts: qcom: purwa-evk: add DP0/DP1 audio playback support
There are stale RPMH votes (BCM votes) observed after GMU suspend. This is because the rpmh stop sequences are skipped during gmu suspend. Fix this and also move GMU to reset state to avoid any further activity. Link: https://lore.kernel.org/all/20260605-assorted-fixes-june-v1-1-2caa04f7287c@oss.qualcomm.com/ Fixes: f248d5d ("drm/msm/a6xx: Fix PDC sleep sequence") Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Signed-off-by: Shivam Rawat <shivrawa@qti.qualcomm.com> Signed-off-by: Bhaskar Gusain <bgusain@qti.qualcomm.com>
FROMLIST: drm/msm/a6xx: Fix stale rpmh votes after suspend
This reverts commit a909091. Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
…f supplies for Glymur" This reverts commit 74e0e79. Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
This reverts commit cd36e04. Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
Before XO refclk is distributed to PCIe/USB/eDP PHYs, it passes through a QREF block. QREF is powered by dedicated LDO rails, and the clkref_en register controls whether refclk is gated through to the PHY side. These clkref controls are different from typical GCC branch clocks: - only a single enable bit is present, without branch-style config bits - regulators must be voted before enable and unvoted after disable Model this as a dedicated clk_ref clock type with custom clk_ops instead of reusing struct clk_branch semantics. Also provide a common registration/probe API so the same clkref model can be reused regardless of where clkref_en registers are placed, e.g. TCSR on glymur and TLMM on SM8750. Link: https://lore.kernel.org/all/20260702-tcsr_qref_0702-v7-0-776f2811b7af@oss.qualcomm.com/ Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
…e to clk_ref helper Replace local clk_branch-based clkref definitions with descriptor-based registration via qcom_clk_ref_probe(). This keeps the glymur driver focused on clock metadata and reuses common runtime logic for regulator handling, enable/disable sequencing, and OF provider wiring. Link: https://lore.kernel.org/all/20260702-tcsr_qref_0702-v7-0-776f2811b7af@oss.qualcomm.com/ Co-developed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
Mahua is based on Glymur but uses a different QREF topology, requiring distinct regulator lists and clock descriptors for its PCIe clock references. Add mahua-specific regulator arrays and clk descriptor table, and use match_data to select the correct descriptor table per compatible string at probe time. Link: https://lore.kernel.org/all/20260702-tcsr_qref_0702-v7-0-776f2811b7af@oss.qualcomm.com/ Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
The QREF block supplies reference clocks to PCIe/USB/UFS PHYs and requires dedicated LDO supplies to operate. The digital control interface for QREF (clkref_en registers) resides in TCSR on x1e80100. Since QREF has no dedicated DT node of its own, these supply properties are placed in the TCSR node which acts as the control interface for QREF. Add a dedicated binding file for qcom,x1e80100-tcsr and document the supply properties. Link: https://lore.kernel.org/all/20260714-hamoa_tcsr_qref_0714_2-v1-1-13047922a376@oss.qualcomm.com/ Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
Replace local clk_branch-based clkref definitions with descriptor-based registration via qcom_clk_ref_probe(). This keeps the x1e80100 driver focused on clock metadata and reuses common runtime logic for regulator handling, enable/disable sequencing, and OF provider wiring. Link: https://lore.kernel.org/all/20260714-hamoa_tcsr_qref_0714_2-v1-2-13047922a376@oss.qualcomm.com/ Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
The QREF block supplies reference clocks to PCIe PHYs and requires dedicated LDO supplies to operate. The digital control interface for QREF (clkref_en registers) resides in TCSR on glymur. Since QREF has no dedicated DT node of its own, these supply properties are placed in the TCSR node which acts as the control interface for QREF. Add a dedicated binding file for qcom,glymur-tcsr and document the supply properties. As this binding will grow to cover more SoCs, mark the required supplies per compatible using an allOf/if/then conditional. Link: https://lore.kernel.org/all/20260702-tcsr_qref_0702-v7-0-776f2811b7af@oss.qualcomm.com/ Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
Mahua shares the same QREF TX/RPT/RX component naming as Glymur, but has a different topology: a single QREF block fed by REFGEN4 only, rather than the two independent blocks fed by REFGEN3 and REFGEN4 on Glymur. Add qcom,mahua-tcsr compatible and document its required supply properties. Note that REFGEN4 is supplied by regulators vdda-refgen3-1p2 and vdda-refgen3-0p9 on Mahua. List: https://lore.kernel.org/all/20260702-tcsr_qref_0702-v7-0-776f2811b7af@oss.qualcomm.com/ Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
…PHY on Glymur The PCIe PHYs on Glymur require a reference voltage provided by REFGEN, which in turn is powered by two LDOs. Since there is no devicetree node for REFGEN, add the vdda-refgen0p9 and vdda-refgen1p2 supplies for each PCIe PHY node. Link: https://lore.kernel.org/all/20260623-phy_refgen-v2-0-4d15983bf91d@oss.qualcomm.com/ Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
The TCSR clkref_en clocks gate the QREF block which provides reference clocks to the PCIe PHYs. Wire up the LDO supplies required by the QREF and refgen blocks on the CRD board. Link: https://lore.kernel.org/all/20260702-tcsr_qref_0702-v7-0-776f2811b7af@oss.qualcomm.com/ Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
Mahua has a different QREF topology from Glymur. Override the TCSR compatible to qcom,mahua-tcsr in mahua.dtsi, and wire up the required LDO supplies on the CRD board. Unlike the other PCIe controllers, PCIe5 PHY on Mahua gets its refclk from the CXO0 pad directly and requires no QREF clkref_en voting. Hence, point its ref clock at RPMH_CXO_CLK. Link: https://lore.kernel.org/all/20260702-tcsr_qref_0702-v7-0-776f2811b7af@oss.qualcomm.com/ Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
Wire up the LDO supplies required by the QREF and refgen blocks on Purwa and Hamoa boards. Purwa's QREF topology is same as Hamoa's, so it reuses the same qcom,x1e80100-tcsr compatible and supply set rather than needing a dedicated one. Link: https://lore.kernel.org/linux-arm-msm/20260714-hamoa_tcsr_qref_0714_2-v1-3-13047922a376@oss.qualcomm.com/ Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
Vote qref in tcsr driver for glymur/mahua/hamoa/purwa
Adds .github/workflows/premerge-pr.yml: a pull_request check that builds every PR into resolute-qcom-devel (the merge ref, build-only) via the reusable build-kernel.yml on main. It lives on this branch because GitHub resolves pull_request workflows from the PR base branch, not the default branch. Depends on the workflow_call interface in #25; do not merge until #25 lands on main. Signed-off-by: Bjordis Collaku <bcollaku@qti.qualcomm.com>
Add the Qualcomm Technologies copyright line above the existing SPDX-License-Identifier tag, matching the header format used in LICENSE.txt and the other .github/workflows/*.yml files. Signed-off-by: Bjordis Collaku <bcollaku@qti.qualcomm.com>
Throwaway change to confirm premerge-pr.yml triggers on PRs into resolute-qcom-devel and reports the required Build check / Build status. Signed-off-by: Bjordis Collaku <bcollaku@qti.qualcomm.com>
Tingwei Zhang (quic-tingweiz)
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Throwaway PR to confirm the pre-merge build check fires on
resolute-qcom-develand reportsBuild check / Buildas a required status.Adds one text file, nothing else. Will close and delete the branch once the check reports.