[893] CortexM: expose RequestTranslationBlockInterrupt for precise bus fault modeling#196
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mamoncha wants to merge 1 commit intorenode:masterfrom
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[893] CortexM: expose RequestTranslationBlockInterrupt for precise bus fault modeling#196mamoncha wants to merge 1 commit intorenode:masterfrom
mamoncha wants to merge 1 commit intorenode:masterfrom
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Related to issue: renode/renode#893 |
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Hi @mamoncha , thanks for the PR. I would suggest, however, that you move it to the TranslationCPU level. There's no reason really to keep it in CortexM. Otherwise - looks good. |
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Peripherals that model synchronous bus faults need to abort the current translation block so the stacked PC in the exception frame points at the faulting instruction, matching real Cortex-M hardware behavior.
Expose the existing tlib mechanism as a public method on CortexM so peripheral models can call it to produce precise faults with correct CFSR.PRECISERR semantics.