┌─────────────────────────────────────────────────────────────────────┐
│ Name : Rickarya Das (ridash) │
│ Domains : Hardware Architecture · Software Engineering · AI/ML │
│ Focus : Silicon → Firmware → Systems → Intelligence │
│ Motto : "From gates to gradients — I build the full stack." │
└─────────────────────────────────────────────────────────────────────┘
I architect systems at every level of the computing stack — from RTL gate logic and RISC-V silicon to full-stack applications and production LLM pipelines. I believe the engineers who understand all three layers will define the next decade of AI hardware.
| Category | Skills & Tools |
|---|---|
| HDL / RTL Design |     |
| Architecture |     |
| FPGA & Simulation |     |
| VLSI EDA |     |
| Protocols |     |
| Verification |    |
| Category | Skills & Tools |
|---|---|
| Languages |        |
| Frontend |    |
| Backend |     |
| Databases |     |
| Systems & OS |     |
| Testing |    |
| Category | Skills & Tools |
|---|---|
| Core Frameworks |     |
| GPU & HPC |     |
| LLM & GenAI |      |
| Hardware AI |     |
| Data & MLOps |     |
| Computer Vision |    |
| Category | Tools |
|---|---|
| Cloud |    |
| Containers |   |
| CI/CD |   |
| IaC |   |
| Observability |   |
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Hardware accelerator for neural computation using bit-serial arithmetic for maximum efficiency at ultra-low power. Demonstrates HW + AI co-design thinking.
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High-throughput systolic array architecture for CNNs — a hardware-AI bridge project benchmarked on FPGA with Vivado synthesis.
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Complete RV32I/RV64I processor implementation with multi-precision arithmetic support — pipeline stages, hazard detection, and full ISA compliance.
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Automated VLSI cell placement optimizer using metaheuristics (simulated annealing + force-directed). Python-based EDA toolchain contribution.
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Custom high-performance CUDA kernels for mathematical and neural operations — matrix multiply, convolution primitives, and attention mechanism acceleration. Bridges AI software with hardware performance engineering.
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┌──────────────────────┐ ┌──────────────────────┐ ┌──────────────────────┐
│ HARDWARE AI │ │ COMPUTER ARCH │ │ VLSI EDA │
│──────────────────────│ │──────────────────────│ │──────────────────────│
│ • Systolic Arrays │ │ • RISC-V Pipelines │ │ • Placement Algos │
│ • Neural Engines │ │ • Multi-Precision │ │ • Sub-7nm Design │
│ • Edge Inference │ │ • Heterogeneous Arch │ │ • DFT / DFM │
│ • LLM Accelerators │ │ • Memory Hierarchy │ │ • Physical Synthesis │
└──────────────────────┘ └──────────────────────┘ └──────────────────────┘
Most engineers work in one layer of the stack. I work in all three — and I know where they intersect.
| Layer | What I bring |
|---|---|
| ⚙️ Silicon / RTL | I design the chips and accelerators that run AI — not just use them |
| 💻 Software / Systems | I write the firmware, drivers, runtimes, and APIs that connect hardware to applications |
| 🤖 AI / ML | I build and optimize models, knowing exactly what the hardware underneath can and cannot do |
This full-stack hardware-to-intelligence perspective is rare — and it's what I bring to every project.
"The best AI systems are designed by engineers who understand the silicon they run on."
