Improve trustzone support: take2#671
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- Derive Copy, Clone, PartialEq, Eq on SauRegion and SauRegionAttribute - SAU::disable_allns(): set CTRL.ALLNS=1, ENABLE=0 (all memory Non-Secure) - SAU::init(regions): disable SAU, program up to 8 regions, re-enable - jump_to_nonsecure(ns_vtor): Secure→Non-Secure boot handoff via BXNS These cover the remaining ARMv8-M TrustZone boot sequence after SAU region programming: disabling the SAU for NS-only systems, bulk-initialising regions without manually looping set_region, and transferring control to the NS image.
Enables non-secure alias for SCB
The values aren't very useful if you cannot access the fields outside the cortex-m crate.
This was referenced Jul 21, 2026
jonathanpallant
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Also moved the BXNS instruction into a global asm block to avoid issues with erasing registers that LLVM wants to use.
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diondokter
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Jul 21, 2026
I don't imagine you could leak a lot from secure mode with those, but we should try and leak nothing.
Contributor
Author
|
I have tested this bootloader function on an STM32U5: #[cortex_m_rt::entry]
fn main() -> ! {
let mut bsp: bsp::SecureBoard = bsp::SecureBoard::new();
// Enable secure fault handler
bsp.scb
.enable(cortex_m::peripheral::scb::Exception::SecureFault);
// Say hello
println!("Hello, this is secure-loader. Configuring peripherals...");
// Configure peripherals
bsp.configure_sau();
println!("...SAU configured");
bsp.set_sram3_nonsecure();
println!("...GTZC1 configured");
let ns_app_base = bsp::hal::ns_addr::FLASH2_START;
println!("Booting NS application at 0x{:08x}...", ns_app_base);
// Boot nonsecure world
unsafe {
cortex_m::asm::bootload_ns(ns_app_base as *const u32, bsp.scb_ns);
}
} |
Contributor
Author
|
See https://developer.arm.com/documentation/dui0801/l/Floating-point-Instructions--32-bit-/VLSTM--A32- |
Contributor
|
That sounds good. Keeps complexity low and it always does the correct thing. The only cost is 2 bytes of flash and 1 clock cycle. Easily worth it |
It should be a NOP if you don't have FPU support. And this is better because someone might have been using the FPU on an EABI target.
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Author
|
These changes also allow a SecureFault handler that looks like this: #[cortex_m_rt::exception]
fn SecureFault() {
println!("SECURE FAULT:");
// Safety: No-one else is using the SAU, so this won't race, plus the registers we want are read-only
let sau = unsafe { &*cortex_m::peripheral::SAU::PTR };
let sfsr = sau.sfsr.read();
if sfsr.sfarvalid() {
println!("- SFAR = {:08x}", sau.sfar.read().address());
}
if sfsr.invep() {
println!("- Invalid Entry Point");
}
if sfsr.invis() {
println!("- Invalid Integrity Signature");
}
if sfsr.inver() {
println!("- Invalid Exception Return");
}
if sfsr.auviol() {
println!("- Attribution Unit Violation");
}
if sfsr.invtran() {
println!("- Invalid Transition");
}
if sfsr.lsperr() {
println!("- Lazy state preservation error");
}
if sfsr.lserr() {
println!("- Lazy state error");
}
loop {}
} |
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This PR merges #648 and #666 into one cohesive whole.