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shreyanshsharma639/README.md

💫 About Me:

  • Working on DFT insertion with a focus on scan-based test methodologies and test-aware RTL design.
  • Involved in DFT insertion at RTL and gate level, scan chain architecture, DFT constraints, and ATPG readiness.
  • Developing Verilog/SystemVerilog RTL with emphasis on clean, synthesizable, and test-friendly design.
  • Open to collaborating on Verilog RTL design, micro-architecture development, RTL and gate-level verification, and DFT projects.
  • Focused on ensuring chips can be tested and trusted before they reach silicon.

🌐 Socials:

Instagram

💻 Tech Stack:

C C++ Verilog SystemVerilog RTL Design DFT Verification Synthesis STA

🛠️ Tools:

ModelSim Vivado Cadence Genus Cadence Modus Siemens Tessent

📊 GitHub Stats:



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  1. DMA-Memory-Subsystem DMA-Memory-Subsystem Public

    A high performance DMA subsystem using AXI4 Full protocols and a custom 16 bank eDRAM architecture. Designed for maximum throughput and minimal leakage, it features predictive bank wakeup logic and…

    Verilog 1 1

  2. -8-BIT-TOTAL-ZERO-COUNTER -8-BIT-TOTAL-ZERO-COUNTER Public

    A digital circuit in Verilog that counts the total number of zeros in an 8-bit input. This project features a chained, ripple-style architecture using custom modules like 4-bit adders and multiplex…

    Verilog

  3. 16_Bit_Comparitor 16_Bit_Comparitor Public

    A 16-bit magnitude comparator in Verilog with a modular, hierarchical design. This project compares two numbers (A, B) and outputs gt/eq/lt signals. It includes a complete testbench and a run.do sc…

    Verilog

  4. 8x3-msb-priiority-encoder- 8x3-msb-priiority-encoder- Public

    8x3 most significant bit priority encoder

    Verilog

  5. eDRAM_1Mb_LowPower eDRAM_1Mb_LowPower Public

    A fully verified, 1-megabyte Embedded DRAM (eDRAM) design with a hybrid core and low-power management unit, written in SystemVerilog.

    Verilog