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Arty: Allow a slower core clk#2

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Megan Wachs (mwachs5) wants to merge 2 commits into
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slower_core_clk
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Arty: Allow a slower core clk#2
Megan Wachs (mwachs5) wants to merge 2 commits into
masterfrom
slower_core_clk

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@mwachs5
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Add a further divided clock for use if designs can't meet 65MHz timing. Also rename the clock frequencies to be more precise.

Ckristian Duran (ckdur) pushed a commit to uec-riscv-team/fpga-shells that referenced this pull request Jan 24, 2024
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