Fix AxiStreamDmaV2Read byte-count handling and expand DMA v2 regression coverage

[bengineerd]

Description

Fix the AxiStreamDmaV2Read GHDL/runtime failure by bounding the AXI byte-count CONV_INTEGER paths and by generating terminal-beat tKeep/tStrb masks directly from slv byte counts. This also expands the axi/dma/rtl/v2/ regression split so the read, write, mux, and FIFO benches each own a distinct behavior surface without excessive overlap.

Details

• Add a shared genTKeep(bytes : slv) overload in axi/axi-stream/rtl/AxiStreamPkg.vhd and use it from axi/dma/rtl/v2/AxiStreamDmaV2Read.vhd so short terminal beats no longer depend on wide-slv to integer conversion.
• Bound the totalBytes conversions in axi/axi4/rtl/AxiPkg.vhd to the burst-size window to avoid the GHDL/std_logic_arith CONV_INTEGER failure that was aborting AxiStreamDmaV2Read.
• Expand tests/axi/dma/test_AxiStreamDmaV2Read.py from the prior expected-failure smoke into passing aligned and short-terminal-beat cases that check payload, tKeep, tDest, tId, observable tUser, and descriptor return behavior.
• Expand tests/axi/dma/test_AxiStreamDmaV2Write.py to cover both a stable single-frame write and a multi-burst write with accepted-AW address monitoring.
• Expand tests/axi/dma/test_AxiStreamDmaV2WriteMux.py to cover descriptor-first, simultaneous-launch, and in-flight data-first arbitration cases, including the ACK_WAIT_BVALID_G path.
• Expand tests/axi/dma/test_AxiStreamDmaV2Fifo.py to cover the integrated FIFO register map and pause-threshold behavior against the live write-buffer count.
• Update the regression handoff/progress notes to remove AxiStreamDmaV2Read from the expected-open list and to document the current v2 DMA bench ownership split.

Related

• Add Verification and Regression Tests for base/ and axi/ #1386
  • Bug was found in this PR. It must be merged first.

[Copilot]

Pull request overview

This PR fixes a GHDL/runtime failure in the AXI-stream DMA v2 read path by avoiding problematic wide CONV_INTEGER conversions and by generating terminal-beat tKeep/tStrb masks directly from the byte-count slv. It also expands the DMA v2 cocotb regressions to cover additional read/write/mux/FIFO behaviors and removes the prior “expected failure” posture for the v2 read test.

Changes:

• Fix DMA v2 read terminal-beat masking by switching to a new genTKeep(bytes : slv) overload and remove dependency on wide-slv-to-integer conversion in AxiStreamDmaV2Read.
• Bound totalBytes conversions in AxiPkg.getAxiLen* to avoid GHDL/std_logic_arith CONV_INTEGER failures.
• Expand and restructure DMA v2 Python/cocotb regression coverage across read, write, write-mux arbitration, and integrated FIFO register/pause-threshold behaviors.

Reviewed changes

Copilot reviewed 7 out of 7 changed files in this pull request and generated 3 comments.

Show a summary per file

File	Description
axi/axi-stream/rtl/AxiStreamPkg.vhd	Adds genTKeep(bytes : slv) overload to generate keep masks without integer conversion.
axi/dma/rtl/v2/AxiStreamDmaV2Read.vhd	Uses the new genTKeep(slv) overload for terminal-beat tKeep/tStrb.
axi/axi4/rtl/AxiPkg.vhd	Bounds CONV_INTEGER conversions to burst-window slices to avoid GHDL failures.
tests/axi/dma/test_AxiStreamDmaV2Read.py	Converts read test from xfail smoke to passing aligned + short-terminal-beat cases and customizes sim build per case.
tests/axi/dma/test_AxiStreamDmaV2Write.py	Expands write regression to include single-frame and multi-burst scenarios with AW acceptance monitoring.
tests/axi/dma/test_AxiStreamDmaV2WriteMux.py	Adds mux arbitration ordering tests (descriptor-first, simultaneous, data-first) and expands parameter sweep.
tests/axi/dma/test_AxiStreamDmaV2Fifo.py	Expands FIFO bench to validate integrated register map and pause-threshold behavior.

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[Copilot]

Pull request overview

Copilot reviewed 8 out of 8 changed files in this pull request and generated no new comments.

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