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Patch Release v2.70.2

16 Apr 19:19
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Patch Release v2.70.2 Latest
Latest

Pull Requests Since v2.70.1

Unlabeled

  1. #1401 - PyRogue parameter alignment cleanup
  2. #1392 - Pgp tests
  3. #1391 - Add cocotb Regression Tests for SSI Modules
  4. #1400 - Add cocotb tests for dsp modules
  5. #1390 - Add cocotb unit tests for protocols/line-codes

Pull Request Details

Add cocotb unit tests for protocols/line-codes
Author: Benjamin Reese bengineerd@users.noreply.github.com
Date: Mon Apr 13 13:53:16 2026 -0700
Pull: #1390 (1730 additions, 527 deletions, 23 files changed)
Branch: slaclab/line-codes-tests

Notes:

Description

Rewrite the protocols/line-codes regression suite into a cleaner package/entity/integration layout, add direct encoder/decoder coverage for all three line-code families, preserve package-level disparity-seed testing with checked-in wrappers, and expand nearby AXI/DMA verification updates already present on verification-2. This branch also drops the temporary planning artifacts under docs/_meta so the PR stays focused on executable verification changes instead of handoff notes.

Details

The line-code test suite is restructured around a shared helper at tests/protocols/line_codes/line_code_test_utils.py with three explicit layers:

  • package-surface benches using checked-in wrappers:
    • protocols/line-codes/wrappers/Code8b10bPkgWrapper.vhd
    • protocols/line-codes/wrappers/Code10b12bPkgWrapper.vhd
    • protocols/line-codes/wrappers/Code12b14bPkgWrapper.vhd
  • direct entity benches:
    • tests/protocols/line_codes/test_Encoder8b10b.py
    • tests/protocols/line_codes/test_Decoder8b10b.py
    • tests/protocols/line_codes/test_Encoder10b12b.py
    • tests/protocols/line_codes/test_Decoder10b12b.py
    • tests/protocols/line_codes/test_Encoder12b14b.py
    • tests/protocols/line_codes/test_Decoder12b14b.py
  • small family integration smokes:
    • tests/protocols/line_codes/test_LineCode8b10bIntegration.py
    • tests/protocols/line_codes/test_LineCode10b12bIntegration.py
    • tests/protocols/line_codes/test_LineCode12b14bIntegration.py

The old duplicated LineCode*Wrapper.vhd adapters and test_LineCode*.py wrapper benches are removed in favor of the cleaner split above.

The new package-level coverage exposed and fixes an illegal-K disparity edge case in protocols/line-codes/rtl/Code12b14bPkg.vhd.

Add cocotb Regression Tests for SSI Modules
Author: Benjamin Reese bengineerd@users.noreply.github.com
Date: Wed Apr 15 13:00:14 2026 -0700
Pull: #1391 (4028 additions, 35 deletions, 24 files changed)
Branch: slaclab/ssi-tests
Issues: #1400

Notes:

Description

Add regression tests for all modules in protocols/ssi.

This PR must be merged after #1400

PRBS Test Configurations (commit 4f181ab)

Added two new parameter sweeps to test_SsiPrbs.py to exercise SsiPrbsTx/SsiPrbsRx across PRBS seed/bus width combinations:

  • seed_eq_bus_width: PRBS_SEED_SIZE_G=512, DATA_BYTES_G=64 (seed width equals output bus width — expected PASS)
  • seed_lt_bus_width: PRBS_SEED_SIZE_G=256, DATA_BYTES_G=64 (seed width less than output bus width — expected to reproduce a suspected SsiPrbsTx bug where the AxiStreamFifoV2 width upsizing mis-packs PRBS data relative to what SsiPrbsRx expects)

To support parameterization, SsiPrbsWrapper.vhd was extended with PRBS_SEED_SIZE_G and DATA_BYTES_G generics (replacing the previous hardcoded 32-bit seed / 16-byte bus).

Pgp tests
Author: Benjamin Reese bengineerd@users.noreply.github.com
Date: Thu Apr 16 11:57:01 2026 -0700
Pull: #1392 (8647 additions, 220 deletions, 92 files changed)
Branch: slaclab/pgp-tests
Issues: #1391

Notes:

Description

Add the next large verification protocols/pgp with checked-in cocotb wrappers and family-organized test packages, plus the small RTL fixes needed to make those regressions pass.

Details

  • protocols/pgp

    • Reorganizes tests into family subpackages:
      • tests/protocols/pgp/pgp2b/
      • tests/protocols/pgp/pgp2fc/
      • tests/protocols/pgp/pgp3/
      • tests/protocols/pgp/pgp4/
      • tests/protocols/pgp/shared/
    • Adds shared helpers:
      • tests/protocols/pgp/pgp_test_utils.py
      • tests/protocols/pgp/pgp2_test_utils.py
      • tests/protocols/pgp/pgp4/pgp4_test_utils.py
      • tests/protocols/pgp/shared/vc_fifo_test_utils.py
      • tests/protocols/pgp/axil_test_utils.py
    • Adds checked-in wrappers across pgp2b, pgp2fc, pgp3, pgp4, and shared VC FIFOs.
    • Adds coverage for:
      • pgp2b: lane, axi, tx/rx path leaves, cell/phy/scheduler wrappers
      • pgp2fc: lane, axi, alignment blocks, tx/rx path leaves, FC fixed-latency checks
      • pgp4: core/core-lite, tx/tx-lite, tx/rx protocol leaves, AXI-Lite, low-speed leaves, and integrated RX CRC-error coverage
      • shared PgpRxVcFifo / PgpTxVcFifo
    • Keeps pgp3 to Pgp3Core coverage only and defers broader pgp3 rollout.

  • Cleanup / repo structure

    • Updates tests/common/regression_utils.py and scripts/build_rtl_instantiation_graph.py to support the newer regression flow.

Related

Add cocotb tests for dsp modules
Author: Benjamin Reese bengineerd@users.noreply.github.com
Date: Mon Apr 13 15:14:47 2026 -0700
Pull: #1400 (2870 additions, 73 deletions, 21 files changed)
Branch: slaclab/dsp-tests
Issues: #1390, #1400

Notes:

Description

Add cocotb-based DSP regression coverage for the generic DSP blocks and fix FIR filter issues uncovered while bringing those tests up. This PR adds reusable DSP test helpers and checked-in wrappers, covers the boxcar, arithmetic, and FIR blocks with parameterized simulations, and aligns the line-code package wrappers with the shared package test harness by exposing invalidK. It also fixes the single-channel FIR path so output valid and sideband timing match the visible data path, initializes FIR tap coefficients from the generic defaults, and corrects the FIR tap accumulator resize to the cascade width.

Details

The new DSP regression coverage adds tests for BoxcarFilter, BoxcarIntegrator, DspAddSub, DspComparator, DspPreSubMult, DspSquareDiffMult, FirFilterTap, FirFilterMultiChannel, FirFilterSingleChannel, and the FIR low-pass and timing wrappers under tests/dsp/generic/, along with shared utilities in tests/dsp/generic/dsp_test_utils.py and new checked-in VHDL wrappers under dsp/generic/wrappers/.

The FIR fixes in dsp/generic/fixed/FirFilterSingleChannel.vhd and dsp/generic/fixed/FirFilterTap.vhd were made to match the behavior exercised by those tests: sideband and obValid now track the actual visible output latency, tap coefficients come up initialized from COEFF_INIT_G, and the accumulator resize uses CASC_WIDTH_G so the cascade path is sized correctly.

DSP Functional RTL Changes

dsp/generic/fixed/FirFilterSingleChannel.vhd
This file was changed to fix output timing alignment in the single-channel FIR.

What changed:

  • Added OUTPUT_DELAY_C and extended the tValid and sideband pipelines to use that visible output delay.
  • Changed the sideband shift from a slice assignment to an explicit loop over the full output-delay pipeline.
  • Moved obValid and sbOut to come from OUTPUT_DELAY_C instead of FILTER_DELAY_C-1.
  • Changed each tap’s datain connection from r.din(i) to the current accepted sample din.

Why:

  • The new DSP tests exposed that the wrapper-visible output latency was one cycle longer than the old valid/sideband bookkeeping assumed.
  • Before this change, dout, obValid, and sbOut could become misaligned, especially in the timing-focused FIR tests.
  • Driving the taps from the accepted input sample and delaying the sideband/valid path to the actual visible output makes the metadata line up with the filtered sample the user sees.

dsp/generic/fixed/FirFilterTap.vhd
This file got two correctness fixes inside the FIR tap primitive.

What changed:

  • The coefficient register now initializes from COEFF_INIT_G instead of zero.
  • The multiply result is resized to CASC_WIDTH_G before adding the cascade value, instead of resizing to PROD_WIDTH_C.

Why:

  • The FIR tests read and exercise startup coefficients immediately. Initializing the tap to zero meant the generic default coefficients were not actually active after reset until reprogrammed.
  • The accumulator width must match the cascade path width. Resizing only to product width is wrong when the cascade bus is wider, and it risks truncation or incorrect arithmetic on the accumulation path.

This PR must be merged after #1390

PyRogue parameter alignment cleanup
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Wed Apr 15 09:33:05 2026 -0700
Pull: #1401 (16902 additions, 16902 deletions, 102 files changed)
Branch: slaclab/pyrogue-formatting

Notes:

Summary

  • Vertically align = signs in self.add(pr.*) parameter blocks across python/surf/
  • Whitespace-only changes; no functional modifications
  • Covers base, devices, ethernet, protocols, xilinx, dsp, and clink modules

Test plan

  • CI regression passes
  • flake8 clean
  • Spot-check diffs show only whitespace changes
Assets 2
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Patch Release v2.70.1

13 Apr 18:00
@ruck314 ruck314
v2.70.1
96172b0
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Patch Release v2.70.1

Pull Requests Since v2.70.0

Unlabeled

  1. #1399 - Add missing PyRogue descriptions to all RemoteVariable/RemoteCommand entries
  2. #1395 - Fix AxiLiteMasterProxy register definitions
  3. #1396 - Fix review findings: bugs, convention violations, register mismatches
  4. #1394 - Add two new programming functions
  5. #1393 - Fix VHDL naming convention issues
  6. #1397 - fix Vivado synthesis hang in Gearbox.vhd shiftReg write

Pull Request Details

Fix VHDL naming convention issues
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Fri Apr 10 12:09:46 2026 -0700
Pull: #1393 (27 additions, 25 deletions, 2 files changed)
Branch: slaclab/fix-vhdl-naming-conventions

Notes:

Description

  • Add missing SLAC company header to AxiLiteRegs.vhd.
  • Rename non-standard AxilRegType/axilR/axilRin to RegType/r/rin and axilComb/axilSeq to comb/seq in StreamPatternTester.vhd.

Add two new programming functions
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Fri Apr 10 08:48:55 2026 -0700
Pull: #1394 (55 additions, 0 deletions, 1 files changed)
Branch: slaclab/sugoi-matrix-config-dev

Notes:

Description

Added two new functions in Sugoi Matrix Configuration python file to ease pixel configuration; need to satisfy the requirement to be able to configure an entire row or a single pixel

Fix AxiLiteMasterProxy register definitions
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Mon Apr 13 10:51:13 2026 -0700
Pull: #1395 (38 additions, 29 deletions, 1 files changed)
Branch: slaclab/AxiLiteMasterProxy-patch

Notes:

Summary

  • Set Resp variable mode='RO' to match VHDL axiSlaveRegisterR at offset 0x04
  • Add description fields to all five RemoteVariable entries in _Regs
  • Add explicit mode='RW' to Rnw, Addr, and Data registers for consistency with Done and Resp which already declare their mode explicitly

Fix review findings: bugs, convention violations, register mismatches
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Fri Apr 10 15:30:13 2026 -0700
Pull: #1396 (29 additions, 28 deletions, 14 files changed)
Branch: slaclab/more-misc-updates

Notes:

Summary

  • Fix combinatorial loop in BoxcarIntegrator signed mode (self-referencing signal)
  • Fix architecture type mismatches (3x mapping->rtl, 1x rtl->mapping)
  • Add missing process label in Pgp4AxiL and fix AXI default response in AxiLiteMasterProxy
  • Fix copy-paste description errors in Ad9681Config and Ina237
  • Fix TmrSem/TmrInject class name collision (TmrSem was inaccessible)
  • Add missing Gthe3Common import to xilinx __init__.py
  • Fix groups parameter type from string to list in AxiVersion and Ad9249
  • Fix DieTempature typo to DieTemperature in Ina237 and Ltc3815
  • Change GigEthReg/XauiReg pauseTime/filtEnable/pauseEnable to read-only

Test plan

  • Python linting passes (flake8 --count python/)
  • Python compilation passes (python -m compileall -f python/)
  • VHDL syntax check passes (make MODULES=$PWD analysis)
  • Regression tests pass (pytest tests/)

fix Vivado synthesis hang in Gearbox.vhd shiftReg write
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Fri Apr 10 21:45:51 2026 -0700
Pull: #1397 (13 additions, 10 deletions, 1 files changed)
Branch: slaclab/Gearbox-vivado-synth-hang-fix

Notes:

Summary

  • The per-bit for-loop introduced in 9ccc0f4 as a workaround for a GHDL --synth dynamic-slice error causes Vivado to treat each iteration as an independent dynamic-index bit write. For wide instances such as Ssr12ToSsr16Gearbox (NUM_CH_G=4 → SLAVE_WIDTH_G=768, SHIFT_WIDTH_C=2305) this inflates synthesis into O(SLAVE_WIDTH_G * SHIFT_WIDTH_C) mux analysis and hangs Vivado synthesis indefinitely (~55 s of no progress, then never completes).
  • Pre-computes the slice bounds into local variables as hi := lo + const. That form satisfies GHDL --synth's "same variable part" check while still presenting Vivado with the variable-base / constant-width slice pattern it recognizes as a single efficient write. bitReverse() is hoisted into a local variable for the same reason.

Background

Bisected against a Simple-rfsoc-4x2-Example build that hangs Vivado synthesis on:

U_Gearbox : entity axi_soc_ultra_plus_core.Ssr12ToSsr16Gearbox
  • surf@v2.66.0, v2.67.0 → synthesis completes
  • surf@v2.68.0, v2.69.0, v2.70.0 → Vivado hangs ~55 s after synth start

Only commit touching Gearbox.vhd / AsyncGearbox.vhd / related files in that window: 9ccc0f4 "resolved GHDL error: cannot extract same variable part for dynamic slice". Reverting just that file on v2.68.0 makes Vivado synthesis complete.

Why this is a compromise between Vivado and GHDL

The write operation is a variable-base, constant-width slice into a shift register. Three forms were considered; each trades off differently between Vivado synthesis and GHDL --synth:

(A) Inline slice — the pre-9ccc0f48 form

v.shiftReg(v.writeIndex+SLAVE_WIDTH_G-1 downto v.writeIndex) := slaveData;
  • Vivado: clean. Recognized as a variable-base / constant-width slice write and synthesized as a single barrel-shifted masked store.
  • GHDL --synth: fails with cannot extract same variable part for dynamic slice. GHDL's synthesis front-end requires both slice bounds to statically resolve to the same base expression plus constant offsets. The inline form (v.writeIndex+SLAVE_WIDTH_G-1 downto v.writeIndex) is two distinct AST sub-expressions that GHDL's matcher cannot unify, even though they are mathematically equivalent. This is the GHDL error 9ccc0f4 was trying to resolve.

(B) Per-bit for loop — the 9ccc0f4 form

for i in 0 to SLAVE_WIDTH_G-1 loop
   v.shiftReg(v.writeIndex + i) := slaveData(i);
end loop;
  • GHDL --synth: accepted. Each bit assignment is a simple dynamic-index write that GHDL handles via a small mux per iteration.
  • Vivado: hangs. Vivado does not collapse the unrolled loop back into a slice write. It treats each of the SLAVE_WIDTH_G iterations as an independent variable-index bit-level assignment into an SHIFT_WIDTH_C-wide register, then tries to prove write disjointness and mux selection for every bit. For SLAVE_WIDTH_G=768, SHIFT_WIDTH_C=2305 the analysis space explodes to ~1.77M mux paths and synthesis never terminates. Narrow gearbox instances happen to survive because the numbers are small enough for Vivado to grind through, but wide ones like Ssr12ToSsr16Gearbox with NUM_CH_G=4 fall off the cliff.

(C) Helper-variable slice — this PR

if (slaveBitOrder = '1') then
   dataIn := bitReverse(slaveData);
else
   dataIn := slaveData;
end if;
lo                       := v.writeIndex;
hi                       := lo + SLAVE_WIDTH_G - 1;
v.shiftReg(hi downto lo) := dataIn;
  • Vivado: still sees the v.shiftReg(hi downto lo) slice form. Vivado's propagation resolves hi - lo to the constant SLAVE_WIDTH_G - 1 at synthesis time and generates the same single barrel-shifted store as form (A). Confirmed experimentally: Simple-rfsoc-4x2-Example synthesis completes past the previous hang point.
  • GHDL --synth: passes its "same variable part" check. Because lo and hi are plain locals with hi := lo + constant, GHDL's matcher directly recognizes both bounds as the same base (lo) plus a static offset. No inline arithmetic to untangle, no per-bit loop to unroll.
  • Cost: two scalar locals (lo, hi) and one slv(SLAVE_WIDTH_G-1 downto 0) local (dataIn) in the process. dataIn hoists bitReverse(slaveData) out of the slice RHS for the same reason — both tools track plain signal writes more reliably than writes whose RHS is a function call inside a dynamic slice.

Simulation equivalence

All three forms produce bit-identical behavior in VHDL simulation (vsim / xsim / GHDL), so the choice is purely a synthesis-path concession. The test_Gearbox and test_AsyncGearbox cocotb tests exercise both the straight and bitReverse (slaveBitOrder='1') paths and pass unchanged — see test plan below.

Alternatives considered and rejected

  • Revert to form (A) and suppress GHDL --synth for Gearbox.vhd: fragile and would regress the purpose of 9ccc0f4 (keeping surf analyzable under GHDL --synth for downstream tooling).
  • Shift-and-mask rewrite (v.shiftReg := (v.shiftReg and not mask) or shifted with two shift_left barrel shifters): works in both tools but adds a second wide barrel shifter and an extra mask term, bloating logic relative to the original slice write. No reason to pay that cost when form (C) matches form (A)'s resource footprint.
  • Wrap the slice in a function writeSliceAt(reg, data, idx): viable fallback if form (C) ever regresses in a future GHDL release — kept as a backup option, not applied here because form (C) already passes both tools today.

Test plan

  • make analysis (GHDL -a VHDL syntax checking) passes — Gearbox.vhd, AsyncGearbox.vhd, all AxiStreamGearbox*, GearboxTb.vhd, Pgp3RxGearboxAligner, SelectIoRxGearboxAligner all analyze cleanly
  • pytest tests/base/general/test_Gearbox.py tests/base/general/test_AsyncGearbox.py → 5/5 passed, including test_Gearbox[bit_reverse_async_reset] which exercises the slaveBitOrder = '1' branch with the hoisted bitReverse()
  • Vivado synthesis of Simple-rfsoc-4x2-Example completes past the previous hang point with this fix applied
  • CI run on this PR should re-confirm both analysis and regressi...
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Minor Release v2.70.0

08 Apr 03:18
@ruck314 ruck314
v2.70.0
3fc57b2
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Minor Release v2.70.0

Pull Requests Since v2.69.0

Bug

  1. #1385 - FirFilterSingleChannel.vhd - Bug fix patch

Unlabeled

  1. #1386 - Add Verification and Regression Tests for base/ and axi/
  2. #1388 - Fix AxiStreamDmaV2Read byte-count handling and expand DMA v2 regression coverage
  3. #1387 - Fix AxiResize upsize bug

Pull Request Details

FirFilterSingleChannel.vhd - Bug fix patch
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Tue Mar 17 09:43:49 2026 -0700
Pull: #1385 (2 additions, 2 deletions, 1 files changed)
Branch: slaclab/fir-axil-patch
Labels: bug

Notes:

Description

Add Verification and Regression Tests for base/ and axi/
Author: Benjamin Reese bengineerd@users.noreply.github.com
Date: Thu Apr 2 13:37:27 2026 -0700
Pull: #1386 (40586 additions, 4319 deletions, 295 files changed)
Branch: slaclab/verification

Notes:

Description

Add the Phase-1 SURF RTL regression baseline for the simulator-friendly base/, axi/, and initial dsp/ modules using the project’s Python-first flow (pytest + cocotb + GHDL + ruckus). This PR adds subsystem-organized cocotb regressions, checked-in IP-integrator wrappers where flat AXI/AXI-Lite/AXIS interfaces are needed, shared regression utilities, and updated planning/progress artifacts under docs/_meta/ so rollout state is recoverable without re-discovery. It also updates CI and local setup so the new regression tiers run reliably in parallel while legacy top-level benches still run in a separate serial pass.

Details

This branch validates the current axi-first Phase-1 queue through the final simulator-friendly axi/ modules and expands base/ coverage across FIFO, sync, delay, RAM, CRC, and general utility blocks, with the first dsp/ leaf now included. It also standardizes common GHDL compile flags, cocotb module discovery helpers, pytest parallel defaults, and the generated RTL queue artifacts used by the planning docs.

Existing Tests

The pre-existing cocotb tests were all folded into the new test structure.
In some cases they were re-written from VHDL driven testbenchs to cocotb.

Known expected-open items on this branch remain:

  • tests/axi/axi4/test_AxiResize.py for the restored 32-bit -> 64-bit upsize case
  • tests/axi/dma/test_AxiStreamDmaV2Read.py due to the current internal CONV_INTEGER assertion under GHDL

Fix AxiResize upsize bug
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Tue Apr 7 19:03:23 2026 -0700
Pull: #1387 (35 additions, 21 deletions, 2 files changed)
Branch: slaclab/fix-axi-resize
Issues: #1386

Notes:

Description

Fix the AXI read upsize path in AxiResize by buffering accepted wide read data before slicing it into narrower downstream beats, and enable the previously xfailed 32-bit to 64-bit resize test now that the RTL bug is fixed.

Details

The read path now stores an accepted master-side beat in a hold register and serves subsequent slave-width slices from that buffered value instead of depending on the live master bus after the initial handshake. This preserves rid, rresp, and rlast correctly across the full sequence of downsliced responses.

The test update removes the xfail marker from the upsize regression case in test_AxiResize.py, since the bug is now fixed.

Related

#1386 must be merged first.

Fix AxiStreamDmaV2Read byte-count handling and expand DMA v2 regression coverage
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Tue Apr 7 20:06:42 2026 -0700
Pull: #1388 (312 additions, 95 deletions, 8 files changed)
Branch: slaclab/fix-dma-read
Issues: #1386

Notes:

Description

Fix the AxiStreamDmaV2Read GHDL/runtime failure by bounding the AXI byte-count CONV_INTEGER paths and by generating terminal-beat tKeep/tStrb masks directly from slv byte counts. This also expands the axi/dma/rtl/v2/ regression split so the read, write, mux, and FIFO benches each own a distinct behavior surface without excessive overlap.

Details

  • Add a shared genTKeep(bytes : slv) overload in axi/axi-stream/rtl/AxiStreamPkg.vhd and use it from axi/dma/rtl/v2/AxiStreamDmaV2Read.vhd so short terminal beats no longer depend on wide-slv to integer conversion.
  • Bound the totalBytes conversions in axi/axi4/rtl/AxiPkg.vhd to the burst-size window to avoid the GHDL/std_logic_arith CONV_INTEGER failure that was aborting AxiStreamDmaV2Read.
  • Expand tests/axi/dma/test_AxiStreamDmaV2Read.py from the prior expected-failure smoke into passing aligned and short-terminal-beat cases that check payload, tKeep, tDest, tId, observable tUser, and descriptor return behavior.
  • Expand tests/axi/dma/test_AxiStreamDmaV2Write.py to cover both a stable single-frame write and a multi-burst write with accepted-AW address monitoring.
  • Expand tests/axi/dma/test_AxiStreamDmaV2WriteMux.py to cover descriptor-first, simultaneous-launch, and in-flight data-first arbitration cases, including the ACK_WAIT_BVALID_G path.
  • Expand tests/axi/dma/test_AxiStreamDmaV2Fifo.py to cover the integrated FIFO register map and pause-threshold behavior against the live write-buffer count.
  • Update the regression handoff/progress notes to remove AxiStreamDmaV2Read from the expected-open list and to document the current v2 DMA bench ownership split.

Related

  • #1386
    • Bug was found in this PR. It must be merged first.
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Minor Release v2.69.0

07 Mar 04:17
@ruck314 ruck314
v2.69.0
c969739
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Minor Release v2.69.0

Pull Requests Since v2.68.0

Unlabeled

  1. #1382 - Adding AxiStreamGearboxTb
  2. #1383 - adding AxiStream Batcher Protocol Version 2
  3. #1380 - bug fix for AxiStreamDmaV2Desc.vhd & AxiStreamDmaV2WriteMux.vhd

Pull Request Details

bug fix for AxiStreamDmaV2Desc.vhd & AxiStreamDmaV2WriteMux.vhd
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Fri Mar 6 20:10:42 2026 -0800
Pull: #1380 (106 additions, 18 deletions, 3 files changed)
Branch: slaclab/AxiStreamDmaV2Desc-patch

Notes:

Description

  • bug fix for the AxiStreamDmaV2Desc wstrb when > 128-bits
    • Refer to "Section A3.4.3 Data read and write structure: Write strobes - Narrow transfers" of the AMBA spec
  • bug fix for AxiStreamDmaV2WriteMux to implement the bvalid/bready properly
  • adding ACK_WAIT_BVALID_G to AxiStreamDmaV2WriteMux

Adding AxiStreamGearboxTb
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Mon Feb 23 14:40:26 2026 -0800
Pull: #1382 (392 additions, 0 deletions, 2 files changed)
Branch: slaclab/AxiStreamGearboxTb
Issues: #1382

Notes:

Description

  • part of getting critical modules in the CI regression testing workflow

adding AxiStream Batcher Protocol Version 2
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Tue Mar 3 08:57:33 2026 -0800
Pull: #1383 (119 additions, 40 deletions, 5 files changed)
Branch: slaclab/AxiStreamBatcherV2
Issues: #1383

Notes:

Description

  • Version 2 of the protocol is nearly identical to Version 1, with the exception of the zero padding previously used in the “Super-Frame Header,” “Sub-Frame Payload,” and “Sub-Frame Tail.”
  • By removing this zero padding, the AXI stream frame on the CPU side no longer needs to account for differences in zero-padding between firmware versions that use different AXI stream widths. This simplifies compatibility, particularly for applications that choose not to use the Rogue unbatcher API to split sub-frames.
  • In addition, this reduces the overall frame size to support faster frame rates
  • https://confluence.slac.stanford.edu/x/L2VlK
  • Pull Request for SW support: slaclab/rogue#1113
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Minor Release v2.68.0

09 Feb 21:18
@ruck314 ruck314
v2.68.0
6ab4790
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Minor Release v2.68.0

Pull Requests Since v2.67.0

Unlabeled

  1. #1378 - migrating the SURF yaml (CPSW only) to amc-carrier-core
  2. #1376 - misc Makefile clean up for cocotb CI testing
  3. #1379 - resolving GHDL specific errors
  4. #1377 - Github CI reog and updates
  5. #1381 - Updates for digital ASIC simulations
  6. #1373 - AxiStreamPkg.vhd Updates
  7. #1374 - AxiLitePkg: adding AxiLiteEndpointArray type
  8. #1372 - Update _Si5345Pages.py

Pull Request Details

Update _Si5345Pages.py
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Mon Feb 2 12:21:35 2026 -0800
Pull: #1372 (0 additions, 3 deletions, 1 files changed)
Branch: slaclab/ruck314-patch-1

Notes:

Description

  • Removed rogue.Version.minVersion('5.4.0') since it is overridden by rogue.Version.minVersion('6.1.0') in python/surf/__init__.py.

AxiStreamPkg.vhd Updates
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Mon Feb 2 12:21:44 2026 -0800
Pull: #1373 (8 additions, 7 deletions, 1 files changed)
Branch: slaclab/AxiStreamPkg-patch

Notes:

Description

AxiLitePkg: adding AxiLiteEndpointArray type
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Mon Feb 2 12:21:50 2026 -0800
Pull: #1374 (6 additions, 1 deletions, 1 files changed)
Branch: slaclab/AxiLiteEndpointArray

Notes:

Description

  • This is a useful type if you have a comb process that operating on multiple AXI-Lite buses on in the same process

misc Makefile clean up for cocotb CI testing
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Tue Feb 3 14:58:10 2026 -0800
Pull: #1376 (231 additions, 65 deletions, 19 files changed)
Branch: slaclab/cocotb-makefile
Issues: #1376

Notes:

Description

Github CI reog and updates
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Fri Feb 6 13:12:03 2026 -0800
Pull: #1377 (55 additions, 58 deletions, 3 files changed)
Branch: slaclab/CI-reorg

Notes:

Description

migrating the SURF yaml (CPSW only) to amc-carrier-core
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Fri Feb 6 13:12:48 2026 -0800
Pull: #1378 (0 additions, 10509 deletions, 31 files changed)
Branch: slaclab/yaml

Notes:

Description

resolving GHDL specific errors
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Mon Feb 9 10:54:40 2026 -0800
Pull: #1379 (76 additions, 72 deletions, 5 files changed)
Branch: slaclab/ghdl-patching

Notes:

Description

Updates for digital ASIC simulations
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Mon Feb 9 11:17:44 2026 -0800
Pull: #1381 (17 additions, 5 deletions, 2 files changed)
Branch: slaclab/digital-asic-patch

Notes:

Description

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Minor Release v2.67.0

21 Jan 20:39
@ruck314 ruck314
v2.67.0
94f1c13
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Minor Release v2.67.0

Pull Requests Since v2.66.0

Unlabeled

  1. #1369 - adding coaxpress/gthUs+ support
  2. #1358 - Fixed Github CI for cocotb v2 + PgpRxVcFifo.vhd Update
  3. #1360 - AxiStreamFifoV2 when CASCADE_SIZE_G>1 using pause flow control update
  4. #1366 - Updates to Saci2ToAxiLite
  5. #1365 - Bug Fix SugoiAxiLitePixelMatrixConfig.vhd
  6. #1368 - bug fixes for AxiStreamMonAxiL.vhd when RST_POLARITY_G='1'
  7. #1370 - AxiStreamGearbox.vhd Update
  8. #1363 - Actually check for LTS timeout in ST_WAIT_C state in Pgp2bRxPhy
  9. #1371 - Update AxiStreamFifoV2.vhd for simulation
  10. #1364 - _SugoiAxiLitePixelMatrixConfig.py Update
  11. #1362 - Update LICENSE.txt
  12. #1361 - Update _CoaXPressAxiL.py

Pull Request Details

Fixed Github CI for cocotb v2 + PgpRxVcFifo.vhd Update
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Mon Dec 8 21:05:42 2025 -0800
Pull: #1358 (346 additions, 262 deletions, 49 files changed)
Branch: slaclab/PgpRxVcFifo-update

Notes:

Description

AxiStreamFifoV2 when CASCADE_SIZE_G>1 using pause flow control update
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Sat Dec 13 11:06:08 2025 -0800
Pull: #1360 (72 additions, 31 deletions, 5 files changed)
Branch: slaclab/AxiStreamFifoV2-cascade-pause

Notes:

Description

Update _CoaXPressAxiL.py
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Mon Dec 15 09:24:49 2025 -0800
Pull: #1361 (0 additions, 1 deletions, 1 files changed)
Branch: slaclab/CoaXPressAxiL-update

Notes:

Description

  • It is useful to expose the RxFsmRst() command to the GUI for debugging

Update LICENSE.txt
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Mon Jan 5 09:30:45 2026 -0800
Pull: #1362 (1 additions, 1 deletions, 1 files changed)
Branch: slaclab/ruck314-patch-1

Notes:

Description

  • Updating for Year 2026

Actually check for LTS timeout in ST_WAIT_C state in Pgp2bRxPhy
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Fri Jan 9 15:33:41 2026 -0800
Pull: #1363 (9 additions, 9 deletions, 1 files changed)
Branch: jgthayer/Pgp2bRxPhy

Notes:

While tracking down an rare error in link establishment for LSSTCam, I found that if there are decode or disparity errors when the LTS timeout reaches FFFFF, then state counter wraps and we don't reset the link. If the link parameters are bad enough, I found I could remain perpetually in the state ST_WAIT_C, and the link never gets reset.

This commit just moves the LTS timeout check before the Decode/Disparity checks.

_SugoiAxiLitePixelMatrixConfig.py Update
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Fri Jan 9 07:48:17 2026 -0800
Pull: #1364 (10 additions, 0 deletions, 1 files changed)
Branch: slaclab/SugoiAxiLitePixelMatrixConfig-update

Notes:

Description

Bug Fix SugoiAxiLitePixelMatrixConfig.vhd
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Fri Jan 9 15:16:24 2026 -0800
Pull: #1365 (27 additions, 16 deletions, 1 files changed)
Branch: slaclab/SugoiAxiLitePixelMatrixConfig-path

Notes:

Description

  • Bug fix for pixel readback return zero
    • Related to the axiSlaveWaitReadTxn() producure reset the rdata back to zero if rready=1
    • Closing out the read transaction at the same time the rdata is updated resolves this issue
  • add gap between switching digital/analog drivers to prevent multiple drivers on the same bus

Updates to Saci2ToAxiLite
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Mon Jan 12 11:18:40 2026 -0800
Pull: #1366 (80 additions, 14 deletions, 4 files changed)
Branch: slaclab/Saci2ToAxiLiteTb-patch

Notes:

Description

  • Clean up cocotb CI to improve positive test coverage.
  • Add support for propagating non-zero AXI-Lite responses to report transaction (TXN) errors to the upstream coordinator.
    • This is implemented by inverting the return OP bit when a non-zero response is detected.
    • The coordinator validates that the returned OP matches the one it sent; a mismatch triggers a memory error that is surfaced to software.

bug fixes for AxiStreamMonAxiL.vhd when RST_POLARITY_G='1'
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Thu Jan 15 08:00:21 2026 -0800
Pull: #1368 (21 additions, 16 deletions, 3 files changed)
Branch: slaclab/AxiStreamMonAxiL-RST_POLARITY_G
Issues: #1367

Notes:

Description

adding coaxpress/gthUs+ support
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Fri Jan 16 16:21:04 2026 -0800
Pull: #1369 (2221 additions, 48 deletions, 9 files changed)
Branch: slaclab/cxp-gth+

Notes:

Description

  • Required for doing CXP over Fiber on a ZCU102 board

AxiStreamGearbox.vhd Update
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Wed Jan 21 12:02:17 2026 -0800
Pull: #1370 (11 additions, 10 deletions, 1 files changed)
Branch: slaclab/AxiStreamGearbox

Notes:

Description

Update AxiStreamFifoV2.vhd for simulation
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Wed Jan 21 12:26:19 2026 -0800
Pull: #1371 (5 additions, 5 deletions, 1 files changed)
Branch: slaclab/ruck314-patch-1
Issues: #326, #353, #356

Notes:

Description

  • For line#326 & line#353~line#356, removed the after TPD_G statement in all
    • in a similar fashion as done in line 215 (async logic)

Contributors

hsandberg-cern
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Minor Release v2.66.0

18 Nov 22:57
@ruck314 ruck314
v2.66.0
fc56630
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Minor Release v2.66.0

Pull Requests Since v2.65.0

Unlabeled

  1. #1356 - PGPv4 Updates and Enchancements
  2. #1352 - Force reset if undefined state for commonly used SURF modules in digital ASIC designs
  3. #1354 - remove the non-ASCII char from source code
  4. #1355 - getOpticalPwr calculation updates
  5. #1351 - Minor Updates to python QSFP
  6. #1348 - Bugfix of latch condition preventing synthesis
  7. #1346 - Fixed the Vivado version checking in ethernet/GigEthCore/lvdsUltraScale/ruckus.tcl
  8. #1357 - Fixed missing TPD_G assignment in signal
  9. #1353 - Update _Pgp4AxiL.py

Pull Request Details

Fixed the Vivado version checking in ethernet/GigEthCore/lvdsUltraScale/ruckus.tcl
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Mon Oct 27 18:29:07 2025 -0700
Pull: #1346 (2 additions, 2 deletions, 1 files changed)
Branch: slaclab/GigEthLvdsUltraScaleCore-patch

Notes:

Description

  • GigEthLvdsUltraScaleCore.dcp was build with Vivado 2022.2

Bugfix of latch condition preventing synthesis
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Tue Oct 28 13:30:31 2025 -0700
Pull: #1348 (5 additions, 2 deletions, 1 files changed)
Branch: slaclab/batchingfifo_fix

Notes:

Fixed bug preventing Vivado synthesis of the code

Description

Regression testing did not catch that a latch was being generated leading to synthesis failure.

Minor Updates to python QSFP
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Thu Nov 6 13:17:43 2025 -0800
Pull: #1351 (10 additions, 4 deletions, 2 files changed)
Branch: slaclab/qsfp-i2c-dev

Notes:

Description

Force reset if undefined state for commonly used SURF modules in digital ASIC designs
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Fri Nov 7 14:20:16 2025 -0800
Pull: #1352 (67 additions, 2 deletions, 20 files changed)
Branch: slaclab/digital-asic-state-others
Issues: #1169

Notes:

Description

  • For ASIC designs it is best to declare a 'Default' state which returns to INIT_S state
    • force INIT_S state if 4-bit r.state is not enum define state
  • removing 'default' on pwrOnRst because it should always be connected on ASIC

Update _Pgp4AxiL.py
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Mon Nov 10 09:49:12 2025 -0800
Pull: #1353 (1 additions, 1 deletions, 1 files changed)
Branch: slaclab/ruck314-patch-1

Notes:

Description

  • Fixed typo in description
  • IEEE 802.3 Clause 74 FEC: "Burst errors of up to 11 bits can be corrected" (not up to 70 bits)

remove the non-ASCII char from source code
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Tue Nov 11 17:26:57 2025 -0800
Pull: #1354 (25 additions, 25 deletions, 21 files changed)
Branch: slaclab/remove-non-ascii-char
Issues: #1354

Notes:

Description

  • While Vivado might not complain, other toolchains (Synposis DC, Cadence Genus, etc) will error if the VHDL has non-ASIC characters in the file
  • This patch replaces all the non-ASIC characters with ASIC characters

getOpticalPwr calculation updates
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Thu Nov 13 09:10:13 2025 -0800
Pull: #1355 (15 additions, 25 deletions, 2 files changed)
Branch: slaclab/getOpticalPwr

Notes:

Description

PGPv4 Updates and Enchancements
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Tue Nov 18 14:15:50 2025 -0800
Pull: #1356 (1263 additions, 385 deletions, 40 files changed)
Branch: slaclab/Pgp4CoreLiteTb

Notes:

Description

  • adding test_Pgp4CoreTb CI
  • adding test_Pgp4CoreLiteTb CI
    • assert error in sim if non-8B AXIS word in Pgp4TxLiteProtocol
  • adding SKIP_EN_G to Pgp4Core.vhd (default TRUE)
  • adding RST_POLARITY_G support to Pgp4AxiL.vhd
  • adding PGP_COMMON_CLK_G & RST_POLARITY_G to Pgp4CoreLite.vhd & Pgp4Core.vhd

Fixed missing TPD_G assignment in signal
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Fri Nov 14 16:51:38 2025 -0800
Pull: #1357 (1 additions, 1 deletions, 1 files changed)
Branch: slaclab/tpdg_batching_fix

Notes:

One of the state signal was missing a TPD_G wait period.

Description

One of the state signal was missing an after TPD_G statement. This should not affect synthesis but might make simulations harder to parse.

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Minor Release v2.65.0

27 Oct 21:18
@ruck314 ruck314
v2.65.0
e01b930
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Minor Release v2.65.0

Pull Requests Since v2.64.0

Unlabeled

  1. #1337 - Axi Stream timing infrastructure
  2. #1345 - Misc PGPv4 Bug Fixes and Enhancements
  3. #1343 - FirFilterSingleChannel Updates
  4. #1340 - Patch for Ads42lb69 Simulation with 7-series
  5. #1344 - HTSP BER Diagnostic Registers
  6. #1342 - updating microblaze/ruckus.tcl
  7. #1338 - HTSP Update: exposing ROGUE_SIM_SIDEBAND_G generic
  8. #1341 - Updates for running sim with MicroblazeBasicCore

Pull Request Details

Axi Stream timing infrastructure
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Mon Oct 27 13:56:46 2025 -0700
Pull: #1337 (883 additions, 1 deletions, 7 files changed)
Branch: slaclab/batching_fifo

Notes:

Included two IPs allowing to batch a user-selectable number of frames together, and to measure the start-of-frame and end-of-frame times between several channels.

Description

This contribution adds two IPs:

  • AxiStreamBatchingFifo.vhd
  • AxiStreamTimer.vhd

AxiStreamBatchingFifo is meant to accumulate a user-defined number of frames to then output them continuously with no pauses. This is important to smooth out streams such as the ones coming from a DMA. Compared to the already present AxiStreamBatcher IP, this implementation does not merge sub-frames into a unique bigger frame, as it is meant to preserve the frame structure.

AxiStreamTimer can monitor several streams for start-of-frame and end-of-frame events. A user selectable number of events can be tracked. This IP can be used to measure latency and iteration interval of HLS IPs.

HTSP Update: exposing ROGUE_SIM_SIDEBAND_G generic
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Fri Oct 3 19:56:33 2025 -0700
Pull: #1338 (6 additions, 4 deletions, 2 files changed)
Branch: slaclab/RogueHtspSim-patch

Notes:

Description

  • Allows users to control where sideband used or not in simulation (instead of always enabled)

Patch for Ads42lb69 Simulation with 7-series
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Wed Oct 8 15:38:42 2025 -0700
Pull: #1340 (129 additions, 0 deletions, 3 files changed)
Branch: slaclab/ads42lb69-sim-patch

Notes:

Description

Updates for running sim with MicroblazeBasicCore
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Thu Oct 9 14:14:59 2025 -0700
Pull: #1341 (3 additions, 0 deletions, 1 files changed)
Branch: slaclab/MicroblazeBasicCore-sim

Notes:

Description

  • Do not include the microblaze in simulation by default

updating microblaze/ruckus.tcl
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Fri Oct 10 15:31:07 2025 -0700
Pull: #1342 (10 additions, 5 deletions, 1 files changed)
Branch: slaclab/MicroblazeBasicCore-patch

Notes:

Description

  • Prevents an error when loading source code if reviewing the design in GUI after batch mode

FirFilterSingleChannel Updates
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Mon Oct 13 13:52:10 2025 -0700
Pull: #1343 (121 additions, 62 deletions, 2 files changed)
Branch: slaclab/FirFilterSingleChannel-updates

Notes:

Description

  • fixed broken FIR sim testbed
  • Resolve the issue where the coefficents in the clk domain and the AxiDualPortRam get out of sync by moving the AXI-lite transactions in the clk domain
  • Update the coeffce default such that the default COEFFICIENTS_C get loaded after reset
  • Adding IBREADY_DEFAULT_G to help optimize the ibReady logic when not used
  • Adding r.din array to help with the big fan out of din due to the Transpose Multiply-Accumulate architecture

HTSP BER Diagnostic Registers
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Mon Oct 20 12:22:49 2025 -0700
Pull: #1344 (99 additions, 0 deletions, 2 files changed)
Branch: slaclab/htsp-ber-mon

Notes:

Description

Misc PGPv4 Bug Fixes and Enhancements
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Thu Oct 23 17:19:44 2025 -0700
Pull: #1345 (168 additions, 28 deletions, 3 files changed)
Branch: slaclab/pgp4-updates

Notes:

Description

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SMURF Patch Release v2.11.4

15 Oct 14:53
@ruck314 ruck314
v2.11.4
ae25e2f

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SMURF Patch Release v2.11.4

Description

  • upgrading to surf@v2.11 for RSSI bug fixes

Full Changelog: v2.11.3...v2.11.4

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Minor Release v2.64.0

02 Oct 00:17
@ruck314 ruck314
v2.64.0
1fe2b35
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Minor Release v2.64.0

Pull Requests Since v2.63.0

Unlabeled

  1. #1301 - Adding FEC optional support to PGPv4 and updates to Scrambler.vhd
  2. #1335 - Fix typo in #1334

Pull Request Details

Adding FEC optional support to PGPv4 and updates to Scrambler.vhd
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Wed Oct 1 14:49:04 2025 -0700
Pull: #1301 (1446 additions, 446 deletions, 30 files changed)
Branch: slaclab/PGPv4-FEC
Issues: #1301

Notes:

Description

Fix typo in #1334
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Tue Sep 30 15:04:42 2025 -0700
Pull: #1335 (4 additions, 4 deletions, 1 files changed)
Branch: slaclab/pgp2fx-gth-fix
Issues: #1334

Notes:

Description

PR #1334 had a typo in the GTH where some signal were named with 'gty'.

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