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chore(G0): update to latest STM32CubeG0 v1.6.2 #2975

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74cad0a
system(g4) update STM32G4xx HAL Drivers to v1.2.7
fpistm May 21, 2026
1252e22
system(g0) update STM32G0xx HAL Drivers to v1.4.7
fpistm May 21, 2026
814fdf4
system(g0): update STM32G0xx CMSIS Drivers to v1.4.5
fpistm May 21, 2026
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11 changes: 10 additions & 1 deletion system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g030xx.h
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Original file line number Diff line number Diff line change
Expand Up @@ -4037,6 +4037,12 @@ typedef struct
#define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
#define RCC_CFGR_SW_2 (0x4UL << RCC_CFGR_SW_Pos) /*!< 0x00000004 */

#define RCC_CFGR_SW_HSISYS (0x00000000UL) /*!< HSISYS oscillator selection as system clock */
#define RCC_CFGR_SW_HSE (0x00000001UL) /*!< HSE oscillator selection as system clock */
#define RCC_CFGR_SW_PLLRCLK (0x00000002UL) /*!< PLLRCLK selection as system clock */
#define RCC_CFGR_SW_LSI (0x00000003UL) /*!< LSI oscillator selection as system clock */
#define RCC_CFGR_SW_LSE (0x00000004UL) /*!< LSE oscillator selection as system clock */

/*!< SWS configuration */
#define RCC_CFGR_SWS_Pos (3U)
#define RCC_CFGR_SWS_Msk (0x7UL << RCC_CFGR_SWS_Pos) /*!< 0x00000038 */
Expand Down Expand Up @@ -4570,6 +4576,9 @@ typedef struct
*/
#define RTC_WAKEUP_SUPPORT
#define RTC_BACKUP_SUPPORT
#define RTC_TAMP_INT_NB 4u
#define RTC_TAMP_NB 2u
#define RTC_BACKUP_NB 5u

/******************** Bits definition for RTC_TR register *******************/
#define RTC_TR_PM_Pos (22U)
Expand Down Expand Up @@ -6309,7 +6318,7 @@ typedef struct

/******************* Bit definition for TIM_CCR5 register *******************/
#define TIM_CCR5_CCR5_Pos (0U)
#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
#define TIM_CCR5_CCR5_Msk (0xFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFF */
#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
#define TIM_CCR5_GC5C1_Pos (29U)
#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */
Expand Down
17 changes: 16 additions & 1 deletion system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g031xx.h
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Original file line number Diff line number Diff line change
Expand Up @@ -3739,6 +3739,9 @@ typedef struct
#define PWR_CR2_PVDRT_0 (0x1UL << PWR_CR2_PVDRT_Pos) /*!< 0x00000010 */
#define PWR_CR2_PVDRT_1 (0x2UL << PWR_CR2_PVDRT_Pos) /*!< 0x00000020 */
#define PWR_CR2_PVDRT_2 (0x4UL << PWR_CR2_PVDRT_Pos) /*!< 0x00000040 */
#define PWR_CR2_PVMEN_DAC_Pos (7U)
#define PWR_CR2_PVMEN_DAC_Msk (0x1UL << PWR_CR2_PVMEN_DAC_Pos) /*!< 0x00000080 */
#define PWR_CR2_PVMEN_DAC PWR_CR2_PVMEN_DAC_Msk /*!< DAC supply voltage monitoring enable */

/******************** Bit definition for PWR_CR3 register ********************/
#define PWR_CR3_EWUP_Pos (0U)
Expand Down Expand Up @@ -3831,6 +3834,9 @@ typedef struct
#define PWR_SR2_PVDO_Pos (11U)
#define PWR_SR2_PVDO_Msk (0x1UL << PWR_SR2_PVDO_Pos) /*!< 0x00000800 */
#define PWR_SR2_PVDO PWR_SR2_PVDO_Msk /*!< Power voltage detector output */
#define PWR_SR2_PVMO_DAC_Pos (15U)
#define PWR_SR2_PVMO_DAC_Msk (0x1UL << PWR_SR2_PVMO_DAC_Pos) /*!< 0x00008000 */
#define PWR_SR2_PVMO_DAC PWR_SR2_PVMO_DAC_Msk /*!< VDDA monitoring output flag */

/******************** Bit definition for PWR_SCR register ********************/
#define PWR_SCR_CWUF_Pos (0U)
Expand Down Expand Up @@ -4217,6 +4223,12 @@ typedef struct
#define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
#define RCC_CFGR_SW_2 (0x4UL << RCC_CFGR_SW_Pos) /*!< 0x00000004 */

#define RCC_CFGR_SW_HSISYS (0x00000000UL) /*!< HSISYS oscillator selection as system clock */
#define RCC_CFGR_SW_HSE (0x00000001UL) /*!< HSE oscillator selection as system clock */
#define RCC_CFGR_SW_PLLRCLK (0x00000002UL) /*!< PLLRCLK selection as system clock */
#define RCC_CFGR_SW_LSI (0x00000003UL) /*!< LSI oscillator selection as system clock */
#define RCC_CFGR_SW_LSE (0x00000004UL) /*!< LSE oscillator selection as system clock */

/*!< SWS configuration */
#define RCC_CFGR_SWS_Pos (3U)
#define RCC_CFGR_SWS_Msk (0x7UL << RCC_CFGR_SWS_Pos) /*!< 0x00000038 */
Expand Down Expand Up @@ -4816,6 +4828,9 @@ typedef struct
*/
#define RTC_WAKEUP_SUPPORT
#define RTC_BACKUP_SUPPORT
#define RTC_TAMP_INT_NB 4u
#define RTC_TAMP_NB 2u
#define RTC_BACKUP_NB 5u

/******************** Bits definition for RTC_TR register *******************/
#define RTC_TR_PM_Pos (22U)
Expand Down Expand Up @@ -6573,7 +6588,7 @@ typedef struct

/******************* Bit definition for TIM_CCR5 register *******************/
#define TIM_CCR5_CCR5_Pos (0U)
#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
#define TIM_CCR5_CCR5_Msk (0xFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFF */
#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
#define TIM_CCR5_GC5C1_Pos (29U)
#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */
Expand Down
17 changes: 16 additions & 1 deletion system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g041xx.h
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Original file line number Diff line number Diff line change
Expand Up @@ -3975,6 +3975,9 @@ typedef struct
#define PWR_CR2_PVDRT_0 (0x1UL << PWR_CR2_PVDRT_Pos) /*!< 0x00000010 */
#define PWR_CR2_PVDRT_1 (0x2UL << PWR_CR2_PVDRT_Pos) /*!< 0x00000020 */
#define PWR_CR2_PVDRT_2 (0x4UL << PWR_CR2_PVDRT_Pos) /*!< 0x00000040 */
#define PWR_CR2_PVMEN_DAC_Pos (7U)
#define PWR_CR2_PVMEN_DAC_Msk (0x1UL << PWR_CR2_PVMEN_DAC_Pos) /*!< 0x00000080 */
#define PWR_CR2_PVMEN_DAC PWR_CR2_PVMEN_DAC_Msk /*!< DAC supply voltage monitoring enable */

/******************** Bit definition for PWR_CR3 register ********************/
#define PWR_CR3_EWUP_Pos (0U)
Expand Down Expand Up @@ -4067,6 +4070,9 @@ typedef struct
#define PWR_SR2_PVDO_Pos (11U)
#define PWR_SR2_PVDO_Msk (0x1UL << PWR_SR2_PVDO_Pos) /*!< 0x00000800 */
#define PWR_SR2_PVDO PWR_SR2_PVDO_Msk /*!< Power voltage detector output */
#define PWR_SR2_PVMO_DAC_Pos (15U)
#define PWR_SR2_PVMO_DAC_Msk (0x1UL << PWR_SR2_PVMO_DAC_Pos) /*!< 0x00008000 */
#define PWR_SR2_PVMO_DAC PWR_SR2_PVMO_DAC_Msk /*!< VDDA monitoring output flag */

/******************** Bit definition for PWR_SCR register ********************/
#define PWR_SCR_CWUF_Pos (0U)
Expand Down Expand Up @@ -4453,6 +4459,12 @@ typedef struct
#define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
#define RCC_CFGR_SW_2 (0x4UL << RCC_CFGR_SW_Pos) /*!< 0x00000004 */

#define RCC_CFGR_SW_HSISYS (0x00000000UL) /*!< HSISYS oscillator selection as system clock */
#define RCC_CFGR_SW_HSE (0x00000001UL) /*!< HSE oscillator selection as system clock */
#define RCC_CFGR_SW_PLLRCLK (0x00000002UL) /*!< PLLRCLK selection as system clock */
#define RCC_CFGR_SW_LSI (0x00000003UL) /*!< LSI oscillator selection as system clock */
#define RCC_CFGR_SW_LSE (0x00000004UL) /*!< LSE oscillator selection as system clock */

/*!< SWS configuration */
#define RCC_CFGR_SWS_Pos (3U)
#define RCC_CFGR_SWS_Msk (0x7UL << RCC_CFGR_SWS_Pos) /*!< 0x00000038 */
Expand Down Expand Up @@ -5114,6 +5126,9 @@ typedef struct
*/
#define RTC_WAKEUP_SUPPORT
#define RTC_BACKUP_SUPPORT
#define RTC_TAMP_INT_NB 4u
#define RTC_TAMP_NB 2u
#define RTC_BACKUP_NB 5u

/******************** Bits definition for RTC_TR register *******************/
#define RTC_TR_PM_Pos (22U)
Expand Down Expand Up @@ -6877,7 +6892,7 @@ typedef struct

/******************* Bit definition for TIM_CCR5 register *******************/
#define TIM_CCR5_CCR5_Pos (0U)
#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
#define TIM_CCR5_CCR5_Msk (0xFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFF */
#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
#define TIM_CCR5_GC5C1_Pos (29U)
#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */
Expand Down
11 changes: 10 additions & 1 deletion system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g050xx.h
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Original file line number Diff line number Diff line change
Expand Up @@ -4056,6 +4056,12 @@ typedef struct
#define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
#define RCC_CFGR_SW_2 (0x4UL << RCC_CFGR_SW_Pos) /*!< 0x00000004 */

#define RCC_CFGR_SW_HSISYS (0x00000000UL) /*!< HSISYS oscillator selection as system clock */
#define RCC_CFGR_SW_HSE (0x00000001UL) /*!< HSE oscillator selection as system clock */
#define RCC_CFGR_SW_PLLRCLK (0x00000002UL) /*!< PLLRCLK selection as system clock */
#define RCC_CFGR_SW_LSI (0x00000003UL) /*!< LSI oscillator selection as system clock */
#define RCC_CFGR_SW_LSE (0x00000004UL) /*!< LSE oscillator selection as system clock */

/*!< SWS configuration */
#define RCC_CFGR_SWS_Pos (3U)
#define RCC_CFGR_SWS_Msk (0x7UL << RCC_CFGR_SWS_Pos) /*!< 0x00000038 */
Expand Down Expand Up @@ -4616,6 +4622,9 @@ typedef struct
*/
#define RTC_WAKEUP_SUPPORT
#define RTC_BACKUP_SUPPORT
#define RTC_TAMP_INT_NB 4u
#define RTC_TAMP_NB 2u
#define RTC_BACKUP_NB 5u

/******************** Bits definition for RTC_TR register *******************/
#define RTC_TR_PM_Pos (22U)
Expand Down Expand Up @@ -6370,7 +6379,7 @@ typedef struct

/******************* Bit definition for TIM_CCR5 register *******************/
#define TIM_CCR5_CCR5_Pos (0U)
#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
#define TIM_CCR5_CCR5_Msk (0xFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFF */
#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
#define TIM_CCR5_GC5C1_Pos (29U)
#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */
Expand Down
17 changes: 16 additions & 1 deletion system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g051xx.h
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Original file line number Diff line number Diff line change
Expand Up @@ -4075,6 +4075,9 @@ typedef struct
#define PWR_CR2_PVDRT_0 (0x1UL << PWR_CR2_PVDRT_Pos) /*!< 0x00000010 */
#define PWR_CR2_PVDRT_1 (0x2UL << PWR_CR2_PVDRT_Pos) /*!< 0x00000020 */
#define PWR_CR2_PVDRT_2 (0x4UL << PWR_CR2_PVDRT_Pos) /*!< 0x00000040 */
#define PWR_CR2_PVMEN_DAC_Pos (7U)
#define PWR_CR2_PVMEN_DAC_Msk (0x1UL << PWR_CR2_PVMEN_DAC_Pos) /*!< 0x00000080 */
#define PWR_CR2_PVMEN_DAC PWR_CR2_PVMEN_DAC_Msk /*!< DAC supply voltage monitoring enable */

/******************** Bit definition for PWR_CR3 register ********************/
#define PWR_CR3_EWUP_Pos (0U)
Expand Down Expand Up @@ -4167,6 +4170,9 @@ typedef struct
#define PWR_SR2_PVDO_Pos (11U)
#define PWR_SR2_PVDO_Msk (0x1UL << PWR_SR2_PVDO_Pos) /*!< 0x00000800 */
#define PWR_SR2_PVDO PWR_SR2_PVDO_Msk /*!< Power voltage detector output */
#define PWR_SR2_PVMO_DAC_Pos (15U)
#define PWR_SR2_PVMO_DAC_Msk (0x1UL << PWR_SR2_PVMO_DAC_Pos) /*!< 0x00008000 */
#define PWR_SR2_PVMO_DAC PWR_SR2_PVMO_DAC_Msk /*!< VDDA monitoring output flag */

/******************** Bit definition for PWR_SCR register ********************/
#define PWR_SCR_CWUF_Pos (0U)
Expand Down Expand Up @@ -4553,6 +4559,12 @@ typedef struct
#define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
#define RCC_CFGR_SW_2 (0x4UL << RCC_CFGR_SW_Pos) /*!< 0x00000004 */

#define RCC_CFGR_SW_HSISYS (0x00000000UL) /*!< HSISYS oscillator selection as system clock */
#define RCC_CFGR_SW_HSE (0x00000001UL) /*!< HSE oscillator selection as system clock */
#define RCC_CFGR_SW_PLLRCLK (0x00000002UL) /*!< PLLRCLK selection as system clock */
#define RCC_CFGR_SW_LSI (0x00000003UL) /*!< LSI oscillator selection as system clock */
#define RCC_CFGR_SW_LSE (0x00000004UL) /*!< LSE oscillator selection as system clock */

/*!< SWS configuration */
#define RCC_CFGR_SWS_Pos (3U)
#define RCC_CFGR_SWS_Msk (0x7UL << RCC_CFGR_SWS_Pos) /*!< 0x00000038 */
Expand Down Expand Up @@ -5191,6 +5203,9 @@ typedef struct
*/
#define RTC_WAKEUP_SUPPORT
#define RTC_BACKUP_SUPPORT
#define RTC_TAMP_INT_NB 4u
#define RTC_TAMP_NB 2u
#define RTC_BACKUP_NB 5u

/******************** Bits definition for RTC_TR register *******************/
#define RTC_TR_PM_Pos (22U)
Expand Down Expand Up @@ -6972,7 +6987,7 @@ typedef struct

/******************* Bit definition for TIM_CCR5 register *******************/
#define TIM_CCR5_CCR5_Pos (0U)
#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
#define TIM_CCR5_CCR5_Msk (0xFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFF */
#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
#define TIM_CCR5_GC5C1_Pos (29U)
#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */
Expand Down
17 changes: 16 additions & 1 deletion system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g061xx.h
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Original file line number Diff line number Diff line change
Expand Up @@ -4311,6 +4311,9 @@ typedef struct
#define PWR_CR2_PVDRT_0 (0x1UL << PWR_CR2_PVDRT_Pos) /*!< 0x00000010 */
#define PWR_CR2_PVDRT_1 (0x2UL << PWR_CR2_PVDRT_Pos) /*!< 0x00000020 */
#define PWR_CR2_PVDRT_2 (0x4UL << PWR_CR2_PVDRT_Pos) /*!< 0x00000040 */
#define PWR_CR2_PVMEN_DAC_Pos (7U)
#define PWR_CR2_PVMEN_DAC_Msk (0x1UL << PWR_CR2_PVMEN_DAC_Pos) /*!< 0x00000080 */
#define PWR_CR2_PVMEN_DAC PWR_CR2_PVMEN_DAC_Msk /*!< DAC supply voltage monitoring enable */

/******************** Bit definition for PWR_CR3 register ********************/
#define PWR_CR3_EWUP_Pos (0U)
Expand Down Expand Up @@ -4403,6 +4406,9 @@ typedef struct
#define PWR_SR2_PVDO_Pos (11U)
#define PWR_SR2_PVDO_Msk (0x1UL << PWR_SR2_PVDO_Pos) /*!< 0x00000800 */
#define PWR_SR2_PVDO PWR_SR2_PVDO_Msk /*!< Power voltage detector output */
#define PWR_SR2_PVMO_DAC_Pos (15U)
#define PWR_SR2_PVMO_DAC_Msk (0x1UL << PWR_SR2_PVMO_DAC_Pos) /*!< 0x00008000 */
#define PWR_SR2_PVMO_DAC PWR_SR2_PVMO_DAC_Msk /*!< VDDA monitoring output flag */

/******************** Bit definition for PWR_SCR register ********************/
#define PWR_SCR_CWUF_Pos (0U)
Expand Down Expand Up @@ -4789,6 +4795,12 @@ typedef struct
#define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
#define RCC_CFGR_SW_2 (0x4UL << RCC_CFGR_SW_Pos) /*!< 0x00000004 */

#define RCC_CFGR_SW_HSISYS (0x00000000UL) /*!< HSISYS oscillator selection as system clock */
#define RCC_CFGR_SW_HSE (0x00000001UL) /*!< HSE oscillator selection as system clock */
#define RCC_CFGR_SW_PLLRCLK (0x00000002UL) /*!< PLLRCLK selection as system clock */
#define RCC_CFGR_SW_LSI (0x00000003UL) /*!< LSI oscillator selection as system clock */
#define RCC_CFGR_SW_LSE (0x00000004UL) /*!< LSE oscillator selection as system clock */

/*!< SWS configuration */
#define RCC_CFGR_SWS_Pos (3U)
#define RCC_CFGR_SWS_Msk (0x7UL << RCC_CFGR_SWS_Pos) /*!< 0x00000038 */
Expand Down Expand Up @@ -5489,6 +5501,9 @@ typedef struct
*/
#define RTC_WAKEUP_SUPPORT
#define RTC_BACKUP_SUPPORT
#define RTC_TAMP_INT_NB 4u
#define RTC_TAMP_NB 2u
#define RTC_BACKUP_NB 5u

/******************** Bits definition for RTC_TR register *******************/
#define RTC_TR_PM_Pos (22U)
Expand Down Expand Up @@ -7276,7 +7291,7 @@ typedef struct

/******************* Bit definition for TIM_CCR5 register *******************/
#define TIM_CCR5_CCR5_Pos (0U)
#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
#define TIM_CCR5_CCR5_Msk (0xFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFF */
#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
#define TIM_CCR5_GC5C1_Pos (29U)
#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */
Expand Down
11 changes: 10 additions & 1 deletion system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g070xx.h
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Original file line number Diff line number Diff line change
Expand Up @@ -4185,6 +4185,12 @@ typedef struct
#define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
#define RCC_CFGR_SW_2 (0x4UL << RCC_CFGR_SW_Pos) /*!< 0x00000004 */

#define RCC_CFGR_SW_HSISYS (0x00000000UL) /*!< HSISYS oscillator selection as system clock */
#define RCC_CFGR_SW_HSE (0x00000001UL) /*!< HSE oscillator selection as system clock */
#define RCC_CFGR_SW_PLLRCLK (0x00000002UL) /*!< PLLRCLK selection as system clock */
#define RCC_CFGR_SW_LSI (0x00000003UL) /*!< LSI oscillator selection as system clock */
#define RCC_CFGR_SW_LSE (0x00000004UL) /*!< LSE oscillator selection as system clock */

/*!< SWS configuration */
#define RCC_CFGR_SWS_Pos (3U)
#define RCC_CFGR_SWS_Msk (0x7UL << RCC_CFGR_SWS_Pos) /*!< 0x00000038 */
Expand Down Expand Up @@ -4768,6 +4774,9 @@ typedef struct
*/
#define RTC_WAKEUP_SUPPORT
#define RTC_BACKUP_SUPPORT
#define RTC_TAMP_INT_NB 4u
#define RTC_TAMP_NB 2u
#define RTC_BACKUP_NB 5u

/******************** Bits definition for RTC_TR register *******************/
#define RTC_TR_PM_Pos (22U)
Expand Down Expand Up @@ -6509,7 +6518,7 @@ typedef struct

/******************* Bit definition for TIM_CCR5 register *******************/
#define TIM_CCR5_CCR5_Pos (0U)
#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
#define TIM_CCR5_CCR5_Msk (0xFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFF */
#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
#define TIM_CCR5_GC5C1_Pos (29U)
#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */
Expand Down
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