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ASoC: rockchip: spdif: Convert to FIELD_PREP
Convert the driver to use FIELD_PREP to increase readability. This also fixes an issue that the SDPIF_CFGR_VDW_MASK was wrong, which didn't have any effects as the only user in the driver updates the other bits at the same time. Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> Link: https://patch.msgid.link/20260203-rockchip-spdif-cleanup-and-bsp-sync-v2-10-4412016cf577@collabora.com Signed-off-by: Mark Brown <broonie@kernel.org>
1 parent 07a7910 commit d94ea90

2 files changed

Lines changed: 32 additions & 34 deletions

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‎sound/soc/rockchip/rockchip_spdif.c‎

Lines changed: 7 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -5,10 +5,11 @@
55
*
66
* Copyright (c) 2014 Rockchip Electronics Co. Ltd.
77
* Author: Jianqun <jay.xu@rock-chips.com>
8-
* Copyright (c) 2015 Collabora Ltd.
8+
* Copyright (c) 2015-2026 Collabora Ltd.
99
* Author: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
1010
*/
1111

12+
#include <linux/bitfield.h>
1213
#include <linux/module.h>
1314
#include <linux/delay.h>
1415
#include <linux/clk.h>
@@ -159,7 +160,7 @@ static int rk_spdif_hw_params(struct snd_pcm_substream *substream,
159160

160161
ret = regmap_update_bits(spdif->regmap, SPDIF_CFGR,
161162
SPDIF_CFGR_CLK_DIV_MASK |
162-
SPDIF_CFGR_HALFWORD_ENABLE |
163+
SPDIF_CFGR_HALFWORD_MASK |
163164
SDPIF_CFGR_VDW_MASK |
164165
SPDIF_CFGR_ADJ_MASK, val);
165166

@@ -177,7 +178,7 @@ static int rk_spdif_trigger(struct snd_pcm_substream *substream,
177178
case SNDRV_PCM_TRIGGER_RESUME:
178179
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
179180
ret = regmap_update_bits(spdif->regmap, SPDIF_DMACR,
180-
SPDIF_DMACR_TDE_ENABLE |
181+
SPDIF_DMACR_TDE_MASK |
181182
SPDIF_DMACR_TDL_MASK,
182183
SPDIF_DMACR_TDE_ENABLE |
183184
SPDIF_DMACR_TDL(16));
@@ -186,21 +187,21 @@ static int rk_spdif_trigger(struct snd_pcm_substream *substream,
186187
return ret;
187188

188189
ret = regmap_update_bits(spdif->regmap, SPDIF_XFER,
189-
SPDIF_XFER_TXS_START,
190+
SPDIF_XFER_TXS_MASK,
190191
SPDIF_XFER_TXS_START);
191192
break;
192193
case SNDRV_PCM_TRIGGER_SUSPEND:
193194
case SNDRV_PCM_TRIGGER_STOP:
194195
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
195196
ret = regmap_update_bits(spdif->regmap, SPDIF_DMACR,
196-
SPDIF_DMACR_TDE_ENABLE,
197+
SPDIF_DMACR_TDE_MASK,
197198
SPDIF_DMACR_TDE_DISABLE);
198199

199200
if (ret != 0)
200201
return ret;
201202

202203
ret = regmap_update_bits(spdif->regmap, SPDIF_XFER,
203-
SPDIF_XFER_TXS_START,
204+
SPDIF_XFER_TXS_MASK,
204205
SPDIF_XFER_TXS_STOP);
205206
break;
206207
default:

‎sound/soc/rockchip/rockchip_spdif.h‎

Lines changed: 25 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@
22
/*
33
* ALSA SoC Audio Layer - Rockchip SPDIF transceiver driver
44
*
5-
* Copyright (c) 2015 Collabora Ltd.
5+
* Copyright (c) 2015-2026 Collabora Ltd.
66
* Author: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
77
*/
88

@@ -13,53 +13,50 @@
1313
* CFGR
1414
* transfer configuration register
1515
*/
16-
#define SPDIF_CFGR_CLK_DIV_SHIFT (16)
17-
#define SPDIF_CFGR_CLK_DIV_MASK (0xff << SPDIF_CFGR_CLK_DIV_SHIFT)
18-
#define SPDIF_CFGR_CLK_DIV(x) ((x-1) << SPDIF_CFGR_CLK_DIV_SHIFT)
16+
#define SPDIF_CFGR_CLK_DIV_MASK GENMASK(23, 16)
17+
#define SPDIF_CFGR_CLK_DIV(x) FIELD_PREP(SPDIF_CFGR_CLK_DIV_MASK, x-1)
1918

2019
#define SPDIF_CFGR_CLR_MASK BIT(7)
21-
#define SPDIF_CFGR_CLR_EN BIT(7)
22-
#define SPDIF_CFGR_CLR_DIS 0
20+
#define SPDIF_CFGR_CLR_EN FIELD_PREP(SPDIF_CFGR_CLR_MASK, 1)
21+
#define SPDIF_CFGR_CLR_DIS FIELD_PREP(SPDIF_CFGR_CLR_MASK, 0)
2322

2423
#define SPDIF_CFGR_CSE_MASK BIT(6)
25-
#define SPDIF_CFGR_CSE_EN BIT(6)
26-
#define SPDIF_CFGR_CSE_DIS 0
24+
#define SPDIF_CFGR_CSE_EN FIELD_PREP(SPDIF_CFGR_CSE_MASK, 1)
25+
#define SPDIF_CFGR_CSE_DIS FIELD_PREP(SPDIF_CFGR_CSE_MASK, 0)
2726

2827
#define SPDIF_CFGR_ADJ_MASK BIT(3)
29-
#define SPDIF_CFGR_ADJ_LEFT_J BIT(3)
30-
#define SPDIF_CFGR_ADJ_RIGHT_J 0
28+
#define SPDIF_CFGR_ADJ_LEFT_J FIELD_PREP(SPDIF_CFGR_ADJ_MASK, 1)
29+
#define SPDIF_CFGR_ADJ_RIGHT_J FIELD_PREP(SPDIF_CFGR_ADJ_MASK, 0)
3130

32-
#define SPDIF_CFGR_HALFWORD_SHIFT 2
33-
#define SPDIF_CFGR_HALFWORD_DISABLE (0 << SPDIF_CFGR_HALFWORD_SHIFT)
34-
#define SPDIF_CFGR_HALFWORD_ENABLE (1 << SPDIF_CFGR_HALFWORD_SHIFT)
31+
#define SPDIF_CFGR_HALFWORD_MASK BIT(2)
32+
#define SPDIF_CFGR_HALFWORD_DISABLE FIELD_PREP(SPDIF_CFGR_HALFWORD_MASK, 0)
33+
#define SPDIF_CFGR_HALFWORD_ENABLE FIELD_PREP(SPDIF_CFGR_HALFWORD_MASK, 1)
3534

36-
#define SPDIF_CFGR_VDW_SHIFT 0
37-
#define SPDIF_CFGR_VDW(x) (x << SPDIF_CFGR_VDW_SHIFT)
38-
#define SDPIF_CFGR_VDW_MASK (0xf << SPDIF_CFGR_VDW_SHIFT)
35+
#define SDPIF_CFGR_VDW_MASK GENMASK(1, 0)
36+
#define SPDIF_CFGR_VDW(x) FIELD_PREP(SDPIF_CFGR_VDW_MASK, x)
3937

40-
#define SPDIF_CFGR_VDW_16 SPDIF_CFGR_VDW(0x0)
41-
#define SPDIF_CFGR_VDW_20 SPDIF_CFGR_VDW(0x1)
42-
#define SPDIF_CFGR_VDW_24 SPDIF_CFGR_VDW(0x2)
38+
#define SPDIF_CFGR_VDW_16 SPDIF_CFGR_VDW(0x0)
39+
#define SPDIF_CFGR_VDW_20 SPDIF_CFGR_VDW(0x1)
40+
#define SPDIF_CFGR_VDW_24 SPDIF_CFGR_VDW(0x2)
4341

4442
/*
4543
* DMACR
4644
* DMA control register
4745
*/
48-
#define SPDIF_DMACR_TDE_SHIFT 5
49-
#define SPDIF_DMACR_TDE_DISABLE (0 << SPDIF_DMACR_TDE_SHIFT)
50-
#define SPDIF_DMACR_TDE_ENABLE (1 << SPDIF_DMACR_TDE_SHIFT)
46+
#define SPDIF_DMACR_TDE_MASK BIT(5)
47+
#define SPDIF_DMACR_TDE_DISABLE FIELD_PREP(SPDIF_DMACR_TDE_MASK, 0)
48+
#define SPDIF_DMACR_TDE_ENABLE FIELD_PREP(SPDIF_DMACR_TDE_MASK, 1)
5149

52-
#define SPDIF_DMACR_TDL_SHIFT 0
53-
#define SPDIF_DMACR_TDL(x) ((x) << SPDIF_DMACR_TDL_SHIFT)
54-
#define SPDIF_DMACR_TDL_MASK (0x1f << SPDIF_DMACR_TDL_SHIFT)
50+
#define SPDIF_DMACR_TDL_MASK GENMASK(4, 0)
51+
#define SPDIF_DMACR_TDL(x) FIELD_PREP(SPDIF_DMACR_TDL_MASK, x)
5552

5653
/*
5754
* XFER
5855
* Transfer control register
5956
*/
60-
#define SPDIF_XFER_TXS_SHIFT 0
61-
#define SPDIF_XFER_TXS_STOP (0 << SPDIF_XFER_TXS_SHIFT)
62-
#define SPDIF_XFER_TXS_START (1 << SPDIF_XFER_TXS_SHIFT)
57+
#define SPDIF_XFER_TXS_MASK BIT(0)
58+
#define SPDIF_XFER_TXS_STOP FIELD_PREP(SPDIF_XFER_TXS_MASK, 0)
59+
#define SPDIF_XFER_TXS_START FIELD_PREP(SPDIF_XFER_TXS_MASK, 1)
6360

6461
#define SPDIF_CFGR (0x0000)
6562
#define SPDIF_SDBLR (0x0004)

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