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platform: mtk: Add afe-platform support for mt8365
Add mt8365 AFE common header and register header files. Add AFE platform for mt8365 audio. Signed-off-by: Andrew Perepech <andrew.perepech@mediatek.com>
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‎src/platform/mt8365/afe-platform.c‎

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// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright(c) 2024 MediaTek. All rights reserved.
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*
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* Author: Andrew Perepech <andrew.perepech@mediatek.com>
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*/
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#include <sof/common.h>
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#include <errno.h>
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#include <sof/drivers/afe-drv.h>
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#include <mt8365-afe-regs.h>
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#include <mt8365-afe-common.h>
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/*
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* AFE: Audio Front-End
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*
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* frontend (memif):
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* memory interface
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* AWB, VULx, TDM_IN (uplink for capture)
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* DLx, TDM_OUT (downlink for playback)
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* backend:
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* TDM In
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* TMD out
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* DMIC
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* GASRC
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* etc.
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* interconn:
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* inter-connection,
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* connect frontends and backends as DSP path
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*/
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static const struct mtk_base_memif_data memif_data[MT8365_MEMIF_NUM] = {
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[MT8365_MEMIF_DL1] = {
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.name = "DL1",
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.id = MT8365_MEMIF_DL1,
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.reg_ofs_base = AFE_DL1_BASE,
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.reg_ofs_cur = AFE_DL1_CUR,
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.reg_ofs_end = AFE_DL1_END,
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.fs_reg = AFE_DAC_CON1,
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.fs_shift = 0,
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.fs_maskbit = 0xf,
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.mono_reg = AFE_DAC_CON1,
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.mono_shift = 21,
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.enable_reg = AFE_DAC_CON0,
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.enable_shift = 1,
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.hd_reg = AFE_MEMIF_PBUF_SIZE,
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.hd_shift = 16,
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.agent_disable_reg = -1,
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.agent_disable_shift = 0,
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.ch_num_reg = -1,
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.ch_num_shift = 0,
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.ch_num_maskbit = 0,
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.msb_reg = -1,
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.msb_shift = 0,
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.msb2_reg = -1,
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.msb2_shift = 0,
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},
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[MT8365_MEMIF_DL2] = {
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.name = "DL2",
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.id = MT8365_MEMIF_DL2,
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.reg_ofs_base = AFE_DL2_BASE,
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.reg_ofs_cur = AFE_DL2_CUR,
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.reg_ofs_end = AFE_DL2_END,
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.fs_reg = AFE_DAC_CON1,
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.fs_shift = 4,
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.fs_maskbit = 0xf,
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.mono_reg = AFE_DAC_CON1,
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.mono_shift = 22,
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.enable_reg = AFE_DAC_CON0,
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.enable_shift = 2,
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.hd_reg = AFE_MEMIF_PBUF_SIZE,
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.hd_shift = 18,
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.agent_disable_reg = -1,
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.agent_disable_shift = 0,
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.ch_num_reg = -1,
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.ch_num_shift = 0,
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.ch_num_maskbit = 0,
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.msb_reg = -1,
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.msb_shift = 0,
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.msb2_reg = -1,
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.msb2_shift = 0,
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},
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[MT8365_MEMIF_TDM_OUT] = {
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.name = "TDM_OUT",
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.id = MT8365_MEMIF_DL2,
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.reg_ofs_base = AFE_HDMI_OUT_BASE,
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.reg_ofs_cur = AFE_HDMI_OUT_CUR,
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.reg_ofs_end = AFE_HDMI_OUT_END,
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.fs_reg = -1,
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.fs_shift = 0,
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.fs_maskbit = 0,
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.mono_reg = -1,
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.mono_shift = 0,
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.enable_reg = AFE_HDMI_OUT_CON0,
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.enable_shift = 0,
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.hd_reg = AFE_MEMIF_PBUF_SIZE,
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.hd_shift = 28,
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.agent_disable_reg = -1,
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.agent_disable_shift = 0,
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.ch_num_reg = -1,
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.ch_num_shift = 0,
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.ch_num_maskbit = 0,
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.msb_reg = -1,
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.msb_shift = 0,
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.msb2_reg = -1,
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.msb2_shift = 0,
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},
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[MT8365_MEMIF_AWB] = {
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.name = "AWB",
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.id = MT8365_MEMIF_AWB,
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.reg_ofs_base = AFE_AWB_BASE,
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.reg_ofs_cur = AFE_AWB_CUR,
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.reg_ofs_end = AFE_AWB_END,
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.fs_reg = AFE_DAC_CON1,
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.fs_shift = 12,
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.fs_maskbit = 0xf,
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.mono_reg = AFE_DAC_CON1,
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.mono_shift = 24,
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.enable_reg = AFE_DAC_CON0,
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.enable_shift = 6,
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.hd_reg = AFE_MEMIF_PBUF_SIZE,
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.hd_shift = 20,
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.agent_disable_reg = -1,
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.agent_disable_shift = 0,
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.ch_num_reg = -1,
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.ch_num_shift = 0,
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.ch_num_maskbit = 0,
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.msb_reg = AFE_MEMIF_MSB,
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.msb_shift = 17,
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.msb2_reg = -1,
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.msb2_shift = 0,
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},
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[MT8365_MEMIF_VUL] = {
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.name = "VUL",
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.id = MT8365_MEMIF_VUL,
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.reg_ofs_base = AFE_VUL_BASE,
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.reg_ofs_cur = AFE_VUL_CUR,
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.reg_ofs_end = AFE_VUL_END,
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.fs_reg = AFE_DAC_CON1,
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.fs_shift = 16,
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.fs_maskbit = 0xf,
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.mono_reg = AFE_DAC_CON1,
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.mono_shift = 27,
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.enable_reg = AFE_DAC_CON0,
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.enable_shift = 3,
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.hd_reg = AFE_MEMIF_PBUF_SIZE,
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.hd_shift = 22,
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.agent_disable_reg = -1,
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.agent_disable_shift = 0,
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.ch_num_reg = -1,
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.ch_num_shift = 0,
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.ch_num_maskbit = 0,
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.msb_reg = AFE_MEMIF_MSB,
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.msb_shift = 20,
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.msb2_reg = -1,
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.msb2_shift = 0,
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},
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[MT8365_MEMIF_VUL2] = {
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.name = "VUL2",
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.id = MT8365_MEMIF_VUL2,
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.reg_ofs_base = AFE_VUL_D2_BASE,
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.reg_ofs_cur = AFE_VUL_D2_CUR,
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.reg_ofs_end = AFE_VUL_D2_END,
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.fs_reg = AFE_DAC_CON0,
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.fs_shift = 20,
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.fs_maskbit = 0xf,
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.mono_reg = AFE_DAC_CON0,
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.mono_shift = 10,
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.enable_reg = AFE_DAC_CON0,
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.enable_shift = 9,
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.hd_reg = AFE_MEMIF_PBUF_SIZE,
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.hd_shift = 14,
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.agent_disable_reg = -1,
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.agent_disable_shift = 0,
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.ch_num_reg = -1,
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.ch_num_shift = 0,
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.ch_num_maskbit = 0,
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.msb_reg = AFE_MEMIF_MSB,
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.msb_shift = 21,
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.msb2_reg = -1,
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.msb2_shift = 0,
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},
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[MT8365_MEMIF_VUL3] = {
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.name = "VUL3",
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.id = MT8365_MEMIF_VUL3,
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.reg_ofs_base = AFE_VUL3_BASE,
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.reg_ofs_cur = AFE_VUL3_CUR,
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.reg_ofs_end = AFE_VUL3_END,
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.fs_reg = AFE_DAC_CON1,
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.fs_shift = 8,
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.fs_maskbit = 0xf,
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.mono_reg = AFE_DAC_CON0,
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.mono_shift = 13,
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.enable_reg = AFE_DAC_CON0,
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.enable_shift = 12,
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.hd_reg = AFE_MEMIF_PBUF2_SIZE,
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.hd_shift = 10,
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.agent_disable_reg = -1,
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.agent_disable_shift = 0,
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.ch_num_reg = -1,
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.ch_num_shift = 0,
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.ch_num_maskbit = 0,
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.msb_reg = AFE_MEMIF_MSB,
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.msb_shift = 27,
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.msb2_reg = -1,
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.msb2_shift = 0,
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},
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[MT8365_MEMIF_TDM_IN] = {
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.name = "TDM_IN",
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.id = MT8365_MEMIF_TDM_IN,
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.reg_ofs_base = AFE_HDMI_IN_2CH_BASE,
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.reg_ofs_cur = AFE_HDMI_IN_2CH_CUR,
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.reg_ofs_end = AFE_HDMI_IN_2CH_END,
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.fs_reg = -1,
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.fs_shift = 0,
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.fs_maskbit = 0,
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.mono_reg = AFE_HDMI_IN_2CH_CON0,
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.mono_shift = 1,
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.enable_reg = AFE_HDMI_IN_2CH_CON0,
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.enable_shift = 0,
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.hd_reg = AFE_MEMIF_PBUF2_SIZE,
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.hd_shift = 8,
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.agent_disable_reg = -1,
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.agent_disable_shift = 0,
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.ch_num_reg = -1,
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.ch_num_shift = 0,
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.ch_num_maskbit = 0,
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.msb_reg = AFE_MEMIF_MSB,
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.msb_shift = 28,
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.msb2_reg = -1,
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.msb2_shift = 0,
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},
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};
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struct mt8365_afe_rate {
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unsigned int rate;
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unsigned int reg_value;
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};
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static const struct mt8365_afe_rate mt8365_afe_rates[] = {
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{
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.rate = 8000,
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.reg_value = 0,
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},
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{
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.rate = 11025,
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.reg_value = 1,
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},
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{
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.rate = 12000,
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.reg_value = 2,
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},
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{
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.rate = 16000,
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.reg_value = 4,
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},
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{
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.rate = 22050,
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.reg_value = 5,
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},
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{
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.rate = 24000,
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.reg_value = 6,
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},
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{
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.rate = 32000,
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.reg_value = 8,
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},
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{
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.rate = 44100,
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.reg_value = 9,
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},
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{
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.rate = 48000,
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.reg_value = 10,
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},
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{
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.rate = 88200,
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.reg_value = 11,
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},
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{
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.rate = 96000,
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.reg_value = 12,
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},
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{
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.rate = 176400,
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.reg_value = 13,
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},
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{
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.rate = 192000,
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.reg_value = 14,
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},
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};
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static unsigned int mt8365_afe_fs_timing(unsigned int rate)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(mt8365_afe_rates); i++)
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if (mt8365_afe_rates[i].rate == rate)
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return mt8365_afe_rates[i].reg_value;
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return -EINVAL;
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}
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static unsigned int mt8365_afe_fs(unsigned int rate, int aud_blk)
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{
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return mt8365_afe_fs_timing(rate);
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}
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static unsigned int mt8365_afe2adsp_addr(unsigned int addr)
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{
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/*TODO : Need apply the address remap */
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return addr;
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}
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static unsigned int mt8365_adsp2afe_addr(unsigned int addr)
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{
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/* TODO : Need apply the address remap */
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return addr;
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}
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struct mtk_base_afe_platform mtk_afe_platform = {
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.base_addr = AFE_REG_BASE,
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.memif_datas = memif_data,
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.memif_size = MT8365_MEMIF_NUM,
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.memif_dl_num = MT8365_MEMIF_DL_NUM,
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.memif_32bit_supported = 0,
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.irq_datas = NULL,
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.irqs_size = 0,
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.dais_size = MT8365_DAI_NUM,
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.afe2adsp_addr = mt8365_afe2adsp_addr,
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.adsp2afe_addr = mt8365_adsp2afe_addr,
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.afe_fs = mt8365_afe_fs,
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.irq_fs = mt8365_afe_fs_timing,
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};

‎src/platform/mt8365/include/platform/mt8365-afe-common.h‎

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/* SPDX-License-Identifier: BSD-3-Clause */
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/*
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* Copyright(c) 2024 MediaTek. All rights reserved.
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*
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* Author: Andrew Perepech <andrew.perepech@mediatek.com>
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*/
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#ifndef _MT_8365_AFE_COMMON_H_
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#define _MT_8365_AFE_COMMON_H_
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/* AFE: the abbreviation for Audio Front End */
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enum {
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MT8365_MEMIF_START,
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MT8365_MEMIF_DL_START = MT8365_MEMIF_START,
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MT8365_MEMIF_DL1 = MT8365_MEMIF_DL_START,
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MT8365_MEMIF_DL2,
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MT8365_MEMIF_TDM_OUT,
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MT8365_MEMIF_DL_END,
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MT8365_MEMIF_UL_START = MT8365_MEMIF_DL_END,
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MT8365_MEMIF_AWB = MT8365_MEMIF_UL_START,
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MT8365_MEMIF_VUL,
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MT8365_MEMIF_VUL2,
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MT8365_MEMIF_VUL3,
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MT8365_MEMIF_TDM_IN,
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MT8365_MEMIF_UL_END,
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MT8365_MEMIF_END = MT8365_MEMIF_UL_END,
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MT8365_MEMIF_DL_NUM = (MT8365_MEMIF_DL_END - MT8365_MEMIF_DL_START),
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MT8365_MEMIF_UL_NUM = (MT8365_MEMIF_UL_END - MT8365_MEMIF_UL_START),
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MT8365_MEMIF_NUM = (MT8365_MEMIF_END - MT8365_MEMIF_START),
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};
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enum {
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MT8365_AFE_IRQ_1,
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MT8365_AFE_IRQ_2,
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MT8365_AFE_IRQ_3,
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MT8365_AFE_IRQ_4,
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MT8365_AFE_IRQ_5,
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MT8365_AFE_IRQ_6,
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MT8365_AFE_IRQ_7,
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MT8365_AFE_IRQ_8,
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MT8365_AFE_IRQ_9,
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MT8365_AFE_IRQ_10,
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MT8365_AFE_IRQ_NUM,
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};
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enum {
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MT8365_AFE_IO_INT_ADDA_OUT,
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MT8365_AFE_IO_2ND_I2S,
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MT8365_AFE_IO_INT_ADDA_IN,
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MT8365_AFE_IO_DMIC,
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MT8365_DAI_NUM,
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};
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#endif /* _MT_8365_AFE_COMMON_H_ */

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