Skip to content

Commit 8db46b4

Browse files
lgirdwoodlgirdwood
authored
Merge pull request #500 from lbetlej/ldo_off_on_power_down
Set SRAM LDO off on power down - additional power gating on D0->D3 path.
2 parents 61e689c + d5c3828 commit 8db46b4

4 files changed

Lines changed: 161 additions & 10 deletions

File tree

‎src/platform/apollolake/include/platform/Makefile.am‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -12,4 +12,5 @@ noinst_HEADERS = \
1212
shim.h \
1313
timer.h \
1414
asm_memory_management.h \
15-
power_down.h
15+
asm_ldo_management.h \
16+
power_down.h

‎src/platform/apollolake/include/platform/asm_ldo_management.h‎

Lines changed: 131 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,131 @@
1+
/*
2+
* Copyright (c) 2018, Intel Corporation
3+
* All rights reserved.
4+
*
5+
* Redistribution and use in source and binary forms, with or without
6+
* modification, are permitted provided that the following conditions are met:
7+
* * Redistributions of source code must retain the above copyright
8+
* notice, this list of conditions and the following disclaimer.
9+
* * Redistributions in binary form must reproduce the above copyright
10+
* notice, this list of conditions and the following disclaimer in the
11+
* documentation and/or other materials provided with the distribution.
12+
* * Neither the name of the Intel Corporation nor the
13+
* names of its contributors may be used to endorse or promote products
14+
* derived from this software without specific prior written permission.
15+
*
16+
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17+
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18+
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19+
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
20+
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21+
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22+
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23+
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24+
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25+
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26+
* POSSIBILITY OF SUCH DAMAGE.
27+
*
28+
* Author: Lech Betlej <lech.betlej@linux.intel.com>
29+
*/
30+
31+
/**
32+
* \file platform/apollolake/include/platform/asm_ldo_management.h
33+
* \brief Macros for controlling LDO state specific for cAVS 1.5
34+
* \author Lech Betlej <lech.betlej@linux.intel.com>
35+
*/
36+
#ifndef ASM_LDO_MANAGEMENT_H
37+
#define ASM_LDO_MANAGEMENT_H
38+
39+
#ifndef ASSEMBLY
40+
#warning "Header can only be used by assembly sources."
41+
#endif
42+
43+
#include <platform/shim.h>
44+
45+
.macro m_cavs_set_ldo_state state, ax
46+
movi \ax, (SHIM_BASE + SHIM_LDOCTL)
47+
s32i \state, \ax, 0
48+
memw
49+
// wait loop > 300ns (min 100ns required)
50+
movi \ax, 128
51+
1 :
52+
addi \ax, \ax, -1
53+
nop
54+
bnez \ax, 1b
55+
.endm
56+
57+
.macro m_cavs_set_hpldo_state state, ax, ay
58+
movi \ax, (SHIM_BASE + SHIM_LDOCTL)
59+
l32i \ay, \ax, 0
60+
61+
movi \ax, ~(SHIM_LDOCTL_HP_SRAM_MASK)
62+
and \ay, \ax, \ay
63+
or \state, \ay, \state
64+
65+
m_cavs_set_ldo_state \state, \ax
66+
.endm
67+
68+
.macro m_cavs_set_lpldo_state state, ax, ay
69+
movi \ax, (SHIM_BASE + SHIM_LDOCTL)
70+
l32i \ay, \ax, 0
71+
// LP SRAM mask
72+
movi \ax, ~(SHIM_LDOCTL_LP_SRAM_MASK)
73+
and \ay, \ax, \ay
74+
or \state, \ay, \state
75+
76+
m_cavs_set_ldo_state \state, \ax
77+
.endm
78+
79+
.macro m_cavs_set_ldo_on_state ax, ay, az
80+
movi \ay, (SHIM_BASE + SHIM_LDOCTL)
81+
l32i \az, \ay, 0
82+
83+
movi \ax, ~(SHIM_LDOCTL_HP_SRAM_MASK | SHIM_LDOCTL_LP_SRAM_MASK)
84+
and \az, \ax, \az
85+
movi \ax, (SHIM_LDOCTL_HP_SRAM_LDO_ON | SHIM_LDOCTL_LP_SRAM_LDO_ON)
86+
or \ax, \az, \ax
87+
88+
m_cavs_set_ldo_state \ax, \ay
89+
.endm
90+
91+
.macro m_cavs_set_ldo_off_state ax, ay, az
92+
// wait loop > 300ns (min 100ns required)
93+
movi \ax, 128
94+
1 :
95+
addi \ax, \ax, -1
96+
nop
97+
bnez \ax, 1b
98+
movi \ay, (SHIM_BASE + SHIM_LDOCTL)
99+
l32i \az, \ay, 0
100+
101+
movi \ax, ~(SHIM_LDOCTL_HP_SRAM_MASK | SHIM_LDOCTL_LP_SRAM_MASK)
102+
and \az, \az, \ax
103+
104+
movi \ax, (SHIM_LDOCTL_HP_SRAM_LDO_OFF | SHIM_LDOCTL_LP_SRAM_LDO_OFF)
105+
or \ax, \ax, \az
106+
107+
s32i \ax, \ay, 0
108+
l32i \ax, \ay, 0
109+
.endm
110+
111+
.macro m_cavs_set_ldo_bypass_state ax, ay, az
112+
// wait loop > 300ns (min 100ns required)
113+
movi \ax, 128
114+
1 :
115+
addi \ax, \ax, -1
116+
nop
117+
bnez \ax, 1b
118+
movi \ay, (SHIM_BASE + SHIM_LDOCTL)
119+
l32i \az, \ay, 0
120+
121+
movi \ax, ~(SHIM_LDOCTL_HP_SRAM_MASK | SHIM_LDOCTL_LP_SRAM_MASK)
122+
and \az, \az, \ax
123+
124+
movi \ax, (SHIM_LDOCTL_HP_SRAM_LDO_BYPASS | SHIM_LDOCTL_LP_SRAM_LDO_BYPASS)
125+
or \ax, \ax, \az
126+
127+
s32i \ax, \ay, 0
128+
l32i \ax, \ay, 0
129+
.endm
130+
131+
#endif /* ASM_LDO_MANAGEMENT_H */

‎src/platform/apollolake/include/platform/shim.h‎

Lines changed: 13 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -145,9 +145,6 @@
145145
#define SHIM_DSPWCTCS_T1A (0x1 << 1) /* Timer 1 armed */
146146
#define SHIM_DSPWCTCS_T0A (0x1 << 0) /* Timer 0 armed */
147147

148-
/** \brief LDO Control */
149-
#define SHIM_LDOCTL 0xA4
150-
151148
/** \brief Clock control */
152149
#define SHIM_CLKCTL 0x78
153150

@@ -219,10 +216,22 @@
219216
/* HP & LP SRAM Power Gating */
220217
#define SHIM_HSPGCTL 0x80
221218
#define SHIM_LSPGCTL 0x84
222-
#define SHIM_SPSREQ 0xa0
219+
#define SHIM_SPSREQ 0xa0
223220

224221
#define SHIM_SPSREQ_RVNNP (0x1 << 0)
225222

223+
/** \brief LDO Control */
224+
#define SHIM_LDOCTL 0xA4
225+
226+
#define SHIM_LDOCTL_HP_SRAM_MASK (3 << 0)
227+
#define SHIM_LDOCTL_LP_SRAM_MASK (3 << 2)
228+
#define SHIM_LDOCTL_HP_SRAM_LDO_ON (3 << 0)
229+
#define SHIM_LDOCTL_LP_SRAM_LDO_ON (3 << 2)
230+
#define SHIM_LDOCTL_HP_SRAM_LDO_BYPASS BIT(0)
231+
#define SHIM_LDOCTL_LP_SRAM_LDO_BYPASS BIT(2)
232+
#define SHIM_LDOCTL_HP_SRAM_LDO_OFF (0 << 0)
233+
#define SHIM_LDOCTL_LP_SRAM_LDO_OFF (0 << 2)
234+
226235
#define SHIM_HSPGISTS 0xb0
227236
#define SHIM_LSPGISTS 0xb4
228237

‎src/platform/apollolake/power_down.S‎

Lines changed: 15 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -34,6 +34,7 @@
3434
* \author Lech Betlej <lech.betlej@linux.intel.com>
3535
*/
3636
#include <platform/asm_memory_management.h>
37+
#include <platform/asm_ldo_management.h>
3738

3839
.section .text, "ax"
3940
.align 64
@@ -86,12 +87,17 @@ power_down:
8687
// if b_enable_lpsram = 0 (bool disable_lpsram) - do not disable lpsram.
8788
beqz b_enable_lpsram, _PD_DISABLE_HPSRAM
8889

89-
9090
_PD_DISABLE_LPSRAM:
91-
m_cavs_lpsram_power_off temp_reg0, temp_reg1, temp_reg2
91+
movi temp_reg0, SHIM_LDOCTL_LP_SRAM_LDO_ON
92+
m_cavs_set_lpldo_state temp_reg0, temp_reg1, temp_reg2
93+
94+
m_cavs_lpsram_power_off temp_reg0, temp_reg1, temp_reg2
95+
96+
movi temp_reg0, SHIM_LDOCTL_LP_SRAM_LDO_OFF
97+
m_cavs_set_lpldo_state temp_reg0, temp_reg1, temp_reg2
9298

93-
// DISABLE_HPSRAM is aligned so there can be zeros between it
94-
// and last instr.
99+
// DISABLE_HPSRAM is aligned so there can be zeros between
100+
//it and last instr.
95101
j _PD_DISABLE_HPSRAM
96102

97103
// workaround for incidental gnu assembler bug - no alignment here
@@ -103,10 +109,14 @@ _PD_DISABLE_HPSRAM:
103109
l32i temp_reg0, pu32_hpsram_mask, 0
104110
beqz temp_reg0, _PD_SLEEP
105111

106-
// TODO: add full support switching off LDO incl. HW W/A
112+
movi temp_reg0, SHIM_LDOCTL_HP_SRAM_LDO_ON
113+
m_cavs_set_hpldo_state temp_reg0, temp_reg1, temp_reg2
114+
// Disable L2 cache in case it would be enabled
107115

108116
m_cavs_hpsram_power_off temp_reg0, temp_reg1, temp_reg2
109117

118+
movi temp_reg0, SHIM_LDOCTL_HP_SRAM_LDO_OFF
119+
m_cavs_set_hpldo_state temp_reg0, temp_reg1, temp_reg2
110120

111121
// For BXT-P we need to deassert VNN request and select slow XTAL
112122
// as clock source

0 commit comments

Comments
 (0)