A zero-copy Linux driver and a userspace interface library for Xilinx's AXI DMA and VDMA IP blocks. These serve as bridges for communication between the processing system and FPGA programmable logic fabric, through one of the DMA ports on the Zynq processing system. Distributed under the MIT License.

Autonomous pre-boot DMA attack hardware implant for M.2 slot based on PicoEVB development board

DMA attacks over PCI Express based on Xilinx Zynq-7000 series SoC

C++ library for AXI DMA with direct and scatter-gather support

Example of transfer UDP packets from AXI DMA with SG mode.

Tutorials or projects example to use Vivado 2019.2 and Vitis

Simple API for working with AXI DMA on Zynq-7000

LTC2324-16 driver for Xilinx AXI-DMA

NVMe Gen4 Host IP DMA with PetaLinux Demo on ZCU106

A practical implementation of AXI DMA on Zynq-7000 (Cora Z7) using High-Performance (HP) Slave ports. Includes a guide on scatter/gather mode configuration with low-level register interfacing required to manage Buffer Descriptors (BDs) without relying on heavy abstractions.

A practical implementation of AXI DMA on Zynq-7000 (Cora Z7) using High-Performance (HP) Slave port. Includes a guide on polling mode configuration, interrupt mode configuration, and scatter-gather mode configuration.

A practical implementation of AXI DMA on Zynq-7000 (Cora Z7) using High-Performance (HP) Slave port. Includes a guide on polling mode configuration and manual L1/L2 cache coherency management.

A practical implementation of AXI DMA on Zynq-7000 (Cora Z7) using High-Performance (HP) Slave port. Includes a guide on interrupt mode configuration and debug setup using ILA.

🚀 Accelerate NVMe Gen4 SSD data transfers using the NVMeG4-IP core and DMA on PetaLinux, achieving high speeds while reducing CPU load.