Competency framework outlining knowledge, skills, and abilities for entry-level semiconductor software and hardware engineers

Config files for my GitHub profile.

Open-source hardware engineering skill library for AI agents, covering PCB, embedded hardware, power, EMC, validation, and board-level design.

Altium Designer Professional Setup — PCB design with schematic capture, interactive routing and 3D board visualization.

Open-source data, checklists, and frameworks behind breezehw.com — BOM pricing at 1K volume, DFM rules, NRE budgets, and FCC/CE/UKCA/RCM/CCC certification navigation for AI hardware founders.

VLSI Design Project as part of Purdue's ECE559 Coursework

University Project Teamwork for Advanced Embedded Systems and Hardware Engineering.

QR-Controlled Geometric Drawing System with precision robotic drawing built with Java for Raspberry Pi and SwiftBot hardware

ELECTRICAL DAMAGE ⚡🔌 PREVENTION SYSTEM

Hiten Dharpure, a Guinness World Record-holding developer. This repository contains the code for an immersive, glassmorphic website showcasing my milestones in AI, robotics, and hardware engineering. Highlights include the world's smallest AI weather station, smallest robot arm, the HastaVaani sign language app, and 3D-printed robotic systems.

Apresentação do perfil.

To explore my work and expertise further, feel free to view my profile here.

HWSphere empowers developers with an intuitive interface for project management, powered by React and Three.js for immersive visualization.

Kleber Lima da Silva - Embedded Systems Engineer | Hardware and Firmware Developer

A SystemVerilog implementation of a 32-bit RV32I RISC-V processor, featuring single-cycle state-driven multicycle (Von Neumann) and pipelined with hazard detection microarchitectures with custom verification testbenches.

Shourov Paul — EEE Graduate | Embedded Systems & IoT Engineer | Robotics Enthusiast from Bangladesh

Verilog FPGA market-data pipeline with sequence integrity, top-of-book state, deterministic latency, risk gating, and self-checking verification.

Verilog FPGA orderbook risk gate with exposure limits, sequence integrity, kill switch, and self-checking verification.

Verilog low-latency stream arbitration crossbar with backpressure handling, latency counters, and self-checking verification.

A miniature 28x20mm pure analog full-bridge driver with active hardware current feedback loop, based on TL494 & SCT63140.