Implementation of a Cryptographic Coprocessor of the PRESENT Lightweight Block Cipher (supporting encryption and decryption, and both 80-bit and 128-bit keys) and some Hardware Trojans, using VHDL
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Jun 27, 2023 - VHDL
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hardware-trojans
Here are 12 public repositories matching this topic...
Dataset of Hardware-Trojan (HT) based Covert Channels (HT-CCs) for the IEEE 802.11 (WiFi) standard.
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Mar 14, 2024
Benchmarking framework for ISPD'23 contest and TCHES'25 paper.
contest eco hardware-security trojans ispd physical-design security-closure hardware-trojans red-vs-blue asap7 tches
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Sep 26, 2025 - Shell
This project is a modified verison of the OpenRISC 1200 open-source processor, designed to estimate the feasibility of using an On-Chip Software Obfuscator to reduce the controllability over software activated Hardware Trojans.
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Apr 11, 2021 - Verilog
A curated paper list and resources on LLM-driven chip design automation and hardware security: RTL/HDL generation, PPA optimization, verification, debugging, trojan/vulnerability analysis, and tool-in-the-loop EDA workflows.
debugging benchmark awesome verification eda survey multi-agent rtl verilog hdl formal-verification hardware-security rag hardware-trojans chip-design llm tool-in-the-loop
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Feb 2, 2026
Supporting material for our RL-based Trojan insertion work at CCS 2022.
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Dec 2, 2023 - Verilog
Architecture informatique post-silicium fusionnant l'intelligence distribuée du mycélium, la frustration géométrique des verres de spin et les modèles de sécurité "zombie" inspirés de l'Ophiocordyceps pour créer des réseaux auto-cicatrisants et résilients
cybersecurity swarm-intelligence mycelium geometric-frustration neuromorphic-computing biomimicry physarum post-silicon hardware-trojans bio-computing lichen-universe lichen-collectives ophiocordyceps-unilateralis
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Jan 16, 2026
A Graph Neural Network framework for detecting hardware Trojans in gate-level .v and .sv netlists; RTL inputs are synthesized via Yosys before classification. Six-stage pipeline (ingestion → parsing → synthesis → graph construction → GNN classification with GCN/GAT/GIN → reporting), with cascade and ensemble inference and per-gate localization.
deep-learning pytorch verilog system-verilog hardware-security electronic-design-automation graph-neural-networks pytorch-geometric hardware-trojans
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Apr 19, 2026 - Python
Includes the code for detecting and classifying hardware trojans in RISC-V cores via machine learning models.
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Jun 19, 2024 - Jupyter Notebook
Distinguishability Analysis Framework for hardware Trojans
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Apr 14, 2026
🛡️ Explore LLM-driven chip design automation and hardware security with curated insights on intelligent EDA and lifecycle security practices.
debugging benchmark awesome verification eda survey multi-agent rtl verilog formal-verification hardware-security rag hardware-trojans chip-design llm tool-in-the-loop
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Apr 22, 2026 - JavaScript
🍄 Explore Bio-Physical architectures that leverage nature-inspired systems to overcome limits in computing and enhance adaptive intelligence.
cybersecurity swarm-intelligence mycelium geometric-frustration neuromorphic-computing biomimicry physarum post-silicon hardware-trojans bio-computing lichen-universe lichen-collectives ophiocordyceps-unilateralis
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Apr 22, 2026
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