Add deterministic decoupling capacitor layout

[justusaugust]

Summary

• carry decoupling-cap group metadata into cap-only partitions, including the main chip and VCC/GND net pair
• copy inherited decoupling net roles from strongly connected main-chip pins so cap-only partitions can still order by the positive-voltage side
• add a dedicated partitionType === "decoupling_caps" path that bypasses generic PackSolver2 and emits a deterministic centered row/stack
• use natural chip-id fallback ordering, side-aware main-pin ordering, preferred fixed rotation, and spacing from the rotated chip body plus protruding pin envelope
• add focused solver coverage with a visualization snapshot, plus partition metadata/net inheritance coverage
• pin circuit-to-svg@0.0.345 directly so the existing full test suite can load convertCircuitJsonToSchematicSimulationSvg

/claim #15

Demo / visual proof

https://github.com/justusaugust/matchpack/releases/download/matchpack-15-demo-2026-05-25/matchpack-15-demo.mp4

The video shows the same pin-envelope regression covered by the new visual snapshot test: current main still routes cap-only partitions through the generic packer, while this patch solves the partition in one step as a centered ordered row with measured centers C1=-1.55, C2=0.00, C10=1.55.

Verification

• bun test tests/PackInnerPartitionsSolver/decoupling-cap-layout.test.ts tests/ChipPartitionsSolver.test.ts — 7 pass, 1 snapshot
• bun test — 21 pass, 1 skip, 0 fail
• bunx tsc --noEmit
• bun run format:check
• bun run build
• git diff --check
• GitHub Actions: test, format-check, and type-check pass on b828c7d

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