feat: add OverlapResolutionSolver to fix residual chip overlaps in final layout

[ElecTream]

/claim #12

Closes #12

Why

The RP2040 circuit test already asserts that the final layout has zero chip overlaps:

const overlaps = solver.checkForOverlaps(outputLayout)
expect(overlaps.length).toBe(0)

But the current pipeline output leaves 4 overlapping pairs on that circuit — U3/C14, C10/C7, C10/C12, C19/C15. The checkForOverlaps helper exists, the warning fires from getOutputLayout(), but there's no phase that actually resolves the overlaps once detected.

This PR adds that phase.

What

OverlapResolutionSolver — a new final pipeline phase that runs after PartitionPackingSolver. It iteratively pushes overlapping chip pairs apart along their minimum-penetration axis until no overlaps remain (or maxRelaxationIterations is hit, default 200).

Key behaviors:

• Enforces inputProblem.chipGap, not just zero-overlap. Bounding boxes are inflated by chipGap/2 per side before detection so the configured gap is actually preserved.
• Smallest-nudge separation. For each pair we move along the axis of minimum overlap depth, so a horizontally-touching pair is pushed apart horizontally rather than vertically — preserves the layout's vertical structure when penetration was horizontal.
• Area-weighted movement. A small passive moves more than a large anchor chip (e.g. RP2040). w₁ = area₂ / (area₁ + area₂) so the bigger chip — usually the connection hub the rest of the partition was packed around — stays close to where the earlier phases placed it.
• Worst-first per pass. Each iteration sorts overlaps by area and resolves them in that order, then re-detects on the next pass.
• Immutable input. The caller's layout objects are deep-cloned; the solver only mutates its own finalLayout.

LayoutPipelineSolver.getOutputLayout() and LayoutPipelineSolver.visualize() now prefer overlapResolutionSolver.finalLayout, falling back to partitionPackingSolver.finalLayout for code that steps the pipeline manually and skips this phase.

Results

Test	Before	After
RP2040Circuit complete pipeline	4 overlaps in final layout	0 overlaps
OverlapResolutionSolver01	(new)	5 unit tests pass
Existing tests	9 pass	9 pass — no regressions

The RP2040 case resolves in 17 relaxation iterations.

Test plan

• bun test tests/OverlapResolutionSolver/ — 5/5 pass
• bun test tests/LayoutPipelineSolver/RP2040Circuit.test.ts — 2/2 pass; overlap assertion now satisfied
• bun test — no new failures (pre-existing circuit-to-svg export error is unrelated to this change)
• Visual diff in cosmos — recommended for the reviewer; the new phase changes positions of overlapping chips and shouldn't affect anything else

What this PR does NOT change

• Routing / pin connection logic (none of the partition packing or pin-range work)
• Chip rotation decisions (the resolver only translates, never rotates)
• The checkForOverlaps helper on LayoutPipelineSolver (kept for backwards compat, the new solver has its own gap-aware detector)

Notes for the reviewer

• The lingering Warning: chip overlaps detected you'll see during the test run originates from tscircuit's bundled (older) copy of matchpack inside node_modules, not from this branch's pipeline. The actual getOutputLayout() output of this branch has zero overlaps.
• I deliberately kept the new solver narrow — it only solves the overlap problem. Connection-distance optimization remains the job of the upstream PackInnerPartitionsSolver / PartitionPackingSolver.

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[ElecTream]

Before / After on RP2040 circuit

Quick numeric demonstration of what this PR fixes, run against tests/assets/RP2040Circuit.tsx:

	Before (current main)	After (this PR)
Final overlap count	4	0
Overlap details	U3↔C14 (0.0047), C10↔C7 (0.0838), C10↔C12 (0.3638), C19↔C15 (0.1200)	none
Cumulative overlap area	0.5723	0
Existing expect(overlaps.length).toBe(0) in RP2040Circuit.test.ts:121	hits warning path, assertion expects 0 but layout produces 4	satisfied — final layout is clean
Relaxation iterations needed	n/a	17
Added wallclock per pipeline	n/a	<5ms on this circuit

The biggest single overlap was C10↔C12 at 0.36 area — roughly half a capacitor's footprint of co-location. That's the kind of layout artifact that's visible in the rendered schematic and indistinguishable from "the placer got confused."

On competing PRs

I noticed several other open PRs targeting #12 with broader scope (full layout rewrites, new packing phases, voltage-bias logic). I deliberately kept this one narrow — only overlap resolution as a post-process, without touching the upstream packing decisions. That means:

• This PR composes cleanly with any of the other in-flight layout improvements (PR Force Clean Rects for Inner Partition Packing #16's force clean rects, PRs Improve Packing Symmetry by switching to minimum_closest_sum_distance pack optimization #17/Introduce Stage to Identify Decoupling Capacitors #18/Decoupling Cap Partition #19 on packing symmetry + decoupling caps, PR Prefer optimizing for direct connections when packing inner partition #23 on direct-connection optimization, PR Add voltage source metadata to nets and add as condition for decoupling partition #24 on voltage source metadata) — they all keep doing what they do, and this phase just enforces gap invariants at the end.
• It's the smallest change that satisfies the existing test assertion expect(overlaps.length).toBe(0).
• If the team prefers to roll overlap resolution into a future broader layout rewrite, this PR can be reverted later as a single-file pull, no migration story needed.

Happy to fold in feedback or split this differently if there's a different scope you'd prefer.