Add M-mode wolfBoot for PolarFire SoC MPFS250TS as an HSS replacement

.github/workflows/test-configs.yml

@@ -527,6 +527,20 @@ jobs:
     with:
       arch: riscv64
       config-file: ./config/examples/polarfire_mpfs250_qspi.config
+  # The UART QSPI programmer is the only code that refreshes the MSS watchdogs
+  # from an S-mode build, where HSS owns the window rather than wolfBoot.
+  microchip_mpfs250_qspi_prog_test:
+    uses: ./.github/workflows/test-build-riscv.yml
+    with:
+      arch: riscv64
+      config-file: ./config/examples/polarfire_mpfs250_qspi.config
+      make-args: UART_QSPI_PROGRAM=1
+  # wolfBoot staged in the L2-LIM rather than DDR, loaded by HSS.
+  microchip_mpfs250_hss_l2lim_test:
+    uses: ./.github/workflows/test-build-riscv.yml
+    with:
+      arch: riscv64
+      config-file: ./config/examples/polarfire_mpfs250_hss_l2lim.config
   # M-mode + LPDDR4 build: generate a CI-only Libero settings stub (all
   # zeros) and point LIBERO_FPGA_CONFIG_DIR at it so MPFS_DDR_INIT actually
   # compiles in CI.  The stub is generated from the HAL sources (not
@@ -539,6 +553,52 @@ jobs:
       config-file: ./config/examples/polarfire_mpfs250_m.config
       pre-build: sh tools/ci/gen_mpfs_libero_stub.sh tools/ci/mpfs_libero_stub
       make-args: LIBERO_FPGA_CONFIG_DIR=tools/ci/mpfs_libero_stub
+  microchip_mpfs250_m_mldsa_test:
+    uses: ./.github/workflows/test-build-riscv.yml
+    with:
+      arch: riscv64
+      config-file: ./config/examples/polarfire_mpfs250_m.config
+      pre-build: sh tools/ci/gen_mpfs_libero_stub.sh tools/ci/mpfs_libero_stub
+      make-args: LIBERO_FPGA_CONFIG_DIR=tools/ci/mpfs_libero_stub SIGN=ML_DSA ML_DSA_LEVEL=5 IMAGE_SIGNATURE_SIZE=4627 IMAGE_HEADER_SIZE=12288 WOLFBOOT_SECTOR_SIZE=0x4000
+  # Boot mode 2: the eNVM wolfBoot linked above the signed manifest and
+  # signed as a wolfBoot image, and the sNVM UBL stub that verifies it.
+  microchip_mpfs250_m_signed_envm_test:
+    uses: ./.github/workflows/test-build-riscv.yml
+    with:
+      arch: riscv64
+      config-file: ./config/examples/polarfire_mpfs250_m.config
+      pre-build: sh tools/ci/gen_mpfs_libero_stub.sh tools/ci/mpfs_libero_stub
+      make-args: LIBERO_FPGA_CONFIG_DIR=tools/ci/mpfs_libero_stub MPFS_ENVM_MANIFEST=1 wolfboot_envm_signed.bin
+  microchip_mpfs250_ubl_test:
+    uses: ./.github/workflows/test-build-riscv.yml
+    with:
+      arch: riscv64
+      config-file: ./config/examples/polarfire_mpfs250_ubl.config
+  # Trust anchor served from sNVM with the production hardenings: ROM-flag
+  # enforcement and the S-mode fence around the System Controller mailbox.
+  microchip_mpfs250_m_snvm_test:
+    uses: ./.github/workflows/test-build-riscv.yml
+    with:
+      arch: riscv64
+      config-file: ./config/examples/polarfire_mpfs250_m.config
+      pre-build: sh tools/ci/gen_mpfs_libero_stub.sh tools/ci/mpfs_libero_stub
+      make-args: LIBERO_FPGA_CONFIG_DIR=tools/ci/mpfs_libero_stub SNVM_KEYSTORE=1 SNVM_KEYSTORE_REQUIRE_ROM=1 MPFS_SCB_SMODE_DENY=1
+  # SBI vendor extension (serial, PUF keys, fenced System Controller services).
+  microchip_mpfs250_m_sbi_test:
+    uses: ./.github/workflows/test-build-riscv.yml
+    with:
+      arch: riscv64
+      config-file: ./config/examples/polarfire_mpfs250_m.config
+      pre-build: sh tools/ci/gen_mpfs_libero_stub.sh tools/ci/mpfs_libero_stub
+      make-args: LIBERO_FPGA_CONFIG_DIR=tools/ci/mpfs_libero_stub MPFS_SBI_VENDOR=1 MPFS_SCB_SMODE_DENY=1 MPFS_SBI_SC_FLASH=1
+  # Encrypted disk image with the AES key unwrapped by the PUF-derived KEK.
+  microchip_mpfs250_m_enc_kek_test:
+    uses: ./.github/workflows/test-build-riscv.yml
+    with:
+      arch: riscv64
+      config-file: ./config/examples/polarfire_mpfs250_m.config
+      pre-build: sh tools/ci/gen_mpfs_libero_stub.sh tools/ci/mpfs_libero_stub
+      make-args: LIBERO_FPGA_CONFIG_DIR=tools/ci/mpfs_libero_stub ENCRYPT=1 ENCRYPT_WITH_AES256=1 CUSTOM_ENCRYPT_KEY=1 SNVM_KEK=1
   microchip_mpfs250_m_qspi_test:
     uses: ./.github/workflows/test-build-riscv.yml
     with:

.gitignore

@@ -637,6 +637,8 @@ tools/unit-tests/stm32g0_write_extract.h
 tools/unit-tests/ct_compare_extract.h
 tools/unit-tests/fdt_memrsv_extract.h
 tools/unit-tests/hifive1_flash_write_extract.h
+tools/unit-tests/mpfs250_wdt_extract.h
+tools/unit-tests/unit-mpfs-wdt
 tools/unit-tests/hifive1_hfrosccfg_extract.h
 tools/unit-tests/keystore_api_extract.h
 tools/unit-tests/keystore_emitted.c

Makefile

@@ -176,7 +176,10 @@ else
       PRIVATE_KEY?=wolfboot_signing_private_key.der
     endif
   endif
-  ifeq ($(FLASH_OTP_KEYSTORE),1)
+  ifeq ($(SNVM_KEYSTORE),1)
+    # PolarFire SoC: trust anchor served from secure NVM at runtime.
+    MPFS_SNVM_OBJ=1
+  else ifeq ($(FLASH_OTP_KEYSTORE),1)
     OBJS+=./src/flash_otp_keystore.o
   else ifeq ($(WOLFBOOT_NO_KEYSTORE),1)
     CFLAGS+=-DWOLFBOOT_NO_KEYSTORE
@@ -188,9 +191,28 @@ else
     WOLFBOOT_SIGN_KEY_DEP=$(PRIVATE_KEY)
   else
     OBJS+=./src/keystore.o
+    # Provisioning build: compiled keys plus the helper that writes them to sNVM.
+    ifeq ($(SNVM_KEYSTORE_PROVISION),1)
+      MPFS_SNVM_OBJ=1
+    endif
   endif
 endif
 
+# PolarFire SoC: sNVM keystore, PUF KEK and the PUF-wrapped encryption-key
+# provider live in one object.
+ifeq ($(SNVM_KEK),1)
+  MPFS_SNVM_OBJ=1
+endif
+ifeq ($(MPFS_SBI_VENDOR),1)
+  MPFS_SNVM_OBJ=1
+endif
+ifeq ($(MPFS_SNVM_DUMP),1)
+  MPFS_SNVM_OBJ=1
+endif
+ifeq ($(MPFS_SNVM_OBJ),1)
+  OBJS+=./hal/mpfs250_snvm.o
+endif
+
 WOLFCRYPT_OBJS:=
 SECURE_OBJS:=
 PUBLIC_KEY_OBJS:=
@@ -503,6 +525,11 @@ ifeq ($(TARGET),rp2350)
     MAIN_TARGET:=include/target.h keytools wolfboot_signing_private_key.der pico-sdk-info
 endif
 
+ifeq ($(TARGET),mpfs250_ubl)
+    # Boot mode 2 stub: verifies the eNVM wolfBoot, there is no application
+    MAIN_TARGET:=wolfboot.bin
+endif
+
 
 ifeq ($(FLASH_OTP_KEYSTORE),1)
     MAIN_TARGET+=tools/keytools/otp/otp-keystore-primer.bin
@@ -756,8 +783,29 @@ factory_wstage1.bin: $(BINASSEMBLE) stage1/loader_stage1.bin wolfboot.bin $(BOOT
 wolfboot_stage1.bin: wolfboot.elf stage1/loader_stage1.bin
 	$(Q) cp stage1/loader_stage1.bin wolfboot_stage1.bin
 
+# PolarFire SoC boot mode 2: sign the eNVM wolfBoot for the UBL stub to verify.  The manifest
+# header goes into the placeholder MPFS_ENVM_MANIFEST=1 links in the last eNVM page, so one
+# mpfsBootmodeProgrammer run programs image and manifest.  See docs/PolarFire.md.
+MPFS_UBL_KEY?=$(PRIVATE_KEY)
+MPFS_ENVM_VERSION?=1
+# The stub is ECC384/SHA384 only, so the manifest size and algorithm do not follow the image's.
+MPFS_ENVM_MANIFEST_SIZE?=512
+wolfboot_envm_signed.bin: wolfboot.elf $(MPFS_UBL_KEY) keytools_check
+	@echo "\t[SIGN] $@"
+	$(Q)(test "$(MPFS_ENVM_MANIFEST)" = "1") || \
+		(echo "wolfboot_envm_signed.bin needs MPFS_ENVM_MANIFEST=1" && false)
+	$(Q)$(OBJCOPY) -O binary --gap-fill 0x00 -R .envm_manifest wolfboot.elf \
+		wolfboot_envm.bin
+	$(Q)$(SIGN_ENV) IMAGE_HEADER_SIZE=$(MPFS_ENVM_MANIFEST_SIZE) \
+		$(SIGN_TOOL) --ecc384 --sha384 wolfboot_envm.bin \
+		$(MPFS_UBL_KEY) $(MPFS_ENVM_VERSION)
+	$(Q)mv wolfboot_envm_v$(MPFS_ENVM_VERSION)_signed.bin $@
+	$(Q)head -c $(MPFS_ENVM_MANIFEST_SIZE) $@ > wolfboot_envm_manifest.bin
+	$(Q)$(OBJCOPY) --update-section .envm_manifest=wolfboot_envm_manifest.bin \
+		wolfboot.elf wolfboot_envm_signed.elf
+
 wolfboot.elf: include/target.h $(LSCRIPT) $(OBJS) $(BINASSEMBLE) $(WOLFBOOT_SIGN_KEY_DEP) FORCE
-	$(Q)(test $(SIGN) = NONE) || (test $(FLASH_OTP_KEYSTORE) = 1) || (test "$(WOLFBOOT_NO_KEYSTORE)" = "1") || (grep -q $(SIGN_ALG) src/keystore.c) || \
+	$(Q)(test $(SIGN) = NONE) || (test $(FLASH_OTP_KEYSTORE) = 1) || (test "$(WOLFBOOT_NO_KEYSTORE)" = "1") || (test "$(SNVM_KEYSTORE)" = "1") || (grep -q $(SIGN_ALG) src/keystore.c) || \
 		(echo "Key mismatch: please run 'make keysclean' to remove all keys if you want to change algorithm" && false)
 	@echo "\t[LD] $@"
 	@echo $(OBJS)
@@ -797,6 +845,8 @@ $(LSCRIPT): $(LSCRIPT_IN) FORCE
 		sed -e "s/@WOLFBOOT_L2LIM_SIZE@/$(WOLFBOOT_L2LIM_SIZE)/g" | \
 		sed -e "s/@L2SRAM_ADDR@/$(L2SRAM_ADDR)/g" | \
 		sed -e "s/@STACK_SIZE_PER_HART@/$(STACK_SIZE_PER_HART)/g" | \
+		sed -e "s/@WOLFBOOT_L2SCRATCH_SIZE@/$(WOLFBOOT_L2SCRATCH_SIZE)/g" | \
+		sed -e "s/@STACK_SIZE@/$(STACK_SIZE)/g" | \
 		sed -e 's/@WOLFHAL_FLASH_EXCLUDE_TEXT@/$(WOLFHAL_FLASH_EXCLUDE_TEXT)/g' | \
 		sed -e 's/@WOLFHAL_FLASH_EXCLUDE_RODATA@/$(WOLFHAL_FLASH_EXCLUDE_RODATA)/g' | \
 		sed -e 's/@WOLFHAL_FLASH_RAM_SECTIONS@/$(WOLFHAL_FLASH_RAM_SECTIONS)/g' \

arch.mk

@@ -1337,9 +1337,23 @@ ifeq ($(ARCH),RISCV64)
     endif
     # Use M-mode specific linker script
     LSCRIPT_IN:=hal/$(TARGET)-m.ld
-    # MPFS DDR init pulls LIBERO_SETTING_* values from a Libero/HSS-generated
-    # fpga_design_config.h. Setting LIBERO_FPGA_CONFIG_DIR enables DDR init
-    # and adds the directory to the include search path.
+    # Boot mode 2: reserve the last eNVM page for the signed manifest the UBL
+    # stub verifies (hal/mpfs250-m.ld); `make wolfboot_envm_signed.bin` fills it.
+    ifeq ($(MPFS_ENVM_MANIFEST),1)
+      CFLAGS+=-DMPFS_ENVM_MANIFEST
+    endif
+    # LIBERO_FPGA_CONFIG_DIR supplies fpga_design_config.h and enables DDR init.
+    # An S-mode OS runs from DDR, so an empty value would silently build a
+    # bootloader with no DDR init at all -- fail instead.
+    ifeq ($(LIBERO_FPGA_CONFIG_DIR),)
+      ifneq (,$(findstring WOLFBOOT_MMODE_SMODE_BOOT,$(CFLAGS_EXTRA) $(CFLAGS)))
+        ifeq ($(filter clean keysclean distclean,$(MAKECMDGOALS)),)
+          $(error WOLFBOOT_MMODE_SMODE_BOOT requires LIBERO_FPGA_CONFIG_DIR: \
+            point it at the board's fpga_design_config directory, e.g. \
+            <hss>/build/boards/mpfs-video-kit/fpga_design_config)
+        endif
+      endif
+    endif
     ifneq ($(LIBERO_FPGA_CONFIG_DIR),)
       CFLAGS+=-DMPFS_DDR_INIT -I$(LIBERO_FPGA_CONFIG_DIR)
       # Generic Cadence DDR controller driver + the MPFS PHY/PLL/training
@@ -1379,6 +1393,15 @@ ifeq ($(ARCH),RISCV64)
     UPDATE_OBJS?=src/update_ram.o
   endif
 
+  # Boot mode 2 UBL stub: LIM-resident, verifies the eNVM wolfBoot manifest
+  # in place and jumps; no update path (hal/mpfs250_ubl.c).
+  ifeq ($(TARGET),mpfs250_ubl)
+    LSCRIPT_IN:=hal/mpfs250_ubl.ld
+    UPDATE_OBJS:=
+    # mcycle rate for hal_get_timer_us(): the stub runs at the reset clock
+    CFLAGS+=-DRISCV_SMODE_TIMER_FREQ=80000000UL
+  endif
+
   # GCC 12+ extension detection (see RISCV 32-bit section above).
   # Extensions go in CFLAGS only; LDFLAGS uses the base march to avoid
   # GCC 15 multilib lookup failures from ISA string decomposition.
@@ -1392,9 +1415,16 @@ ifeq ($(ARCH),RISCV64)
     CFLAGS+=-march=rv64imac$(RISCV64_ZICSR)$(RISCV64_ZIFENCEI) -mabi=lp64 -mcmodel=medany
     LDFLAGS+=-march=rv64imac -mabi=lp64 -mcmodel=medany
   else
-    # U54 cores: rv64gc (with FPU)
-    CFLAGS+=-march=rv64imafd$(RISCV64_ZICSR)$(RISCV64_ZIFENCEI) -mabi=lp64d -mcmodel=medany
-    LDFLAGS+=-march=rv64imafd -mabi=lp64d -mcmodel=medany
+    # U54.  Microchip's CAL archive is built rv64imac soft-float, so a build
+    # that links it has to match; rv64imac not rv64imafd because the toolchain
+    # ships no F/D-ISA + soft-float multilib.  wolfBoot emits no FP either way.
+    ifeq ($(MPFS_ATHENA),1)
+      CFLAGS+=-march=rv64imac$(RISCV64_ZICSR)$(RISCV64_ZIFENCEI) -mabi=lp64 -mcmodel=medany
+      LDFLAGS+=-march=rv64imac -mabi=lp64 -mcmodel=medany
+    else
+      CFLAGS+=-march=rv64imafd$(RISCV64_ZICSR)$(RISCV64_ZIFENCEI) -mabi=lp64d -mcmodel=medany
+      LDFLAGS+=-march=rv64imafd -mabi=lp64d -mcmodel=medany
+    endif
 
     # FDT support for DDR S-mode (not needed for L2-LIM bare-metal boot)
     ifneq ($(MPFS_L2LIM),1)

config/examples/polarfire_mpfs250.config

@@ -66,8 +66,12 @@ WOLFBOOT_LOAD_ADDRESS?=0x8E000000
 # Using update_disk loader we just need to specify the partition number or A/B
 WOLFBOOT_NO_PARTITIONS=1
 WOLFBOOT_RAMBOOT_MAX_SIZE=0x80000000
-CFLAGS_EXTRA+=-DBOOT_PART_A=1
-CFLAGS_EXTRA+=-DBOOT_PART_B=2
+# 0-based GPT index.  Index 1 on the stock Microchip layout is the BIOS-boot
+# partition HSS reads its own payload from, leaving one usable boot slot: A and
+# B name the same one, so failover has no rollback target until a p4 is added.
+# For a two-slot layout see polarfire_mpfs250_m.config (A=0, B=1).
+CFLAGS_EXTRA+=-DBOOT_PART_A=0
+CFLAGS_EXTRA+=-DBOOT_PART_B=0
 
 # ============================================================================
 # Optional: read the signed image from a file on a read-only filesystem

config/examples/polarfire_mpfs250_m.config

@@ -77,18 +77,23 @@ CFLAGS_EXTRA+=-DWOLFBOOT_MMODE_SMODE_BOOT
 DISK_SDCARD?=1
 DISK_EMMC?=0
 
-# wolfBoot in L2 SRAM (256KB available)
+# wolfBoot in L2 SRAM: all 4 scratchpad ways (0x0A000000 - 0x0A07FFFF)
 WOLFBOOT_ORIGIN?=0x0A000000
+WOLFBOOT_L2SCRATCH_SIZE?=512k
+
+# Boot-hart stack, sized for ML-DSA-87 verify on top of the two
+# IMAGE_HEADER_SIZE buffers update_disk.c puts on the stack.  ECC384 needs less.
+STACK_SIZE?=64k
 
 # 4KB sector size (SD card flow is partition-based, not flash-erase-based)
 WOLFBOOT_SECTOR_SIZE?=0x1000
 
 # Scratch address where the signed FIT image is staged before signature
-# verification + FIT parse.  Placed early in DDR (32 MB into 2 GB) so we
-# stay within the fully-trained region near 0x80000000 - the LPDDR4 TIP
-# completes BCLK_SCLK only (train_stat=0x1) on this Video Kit and higher
-# DDR addresses (e.g. 0x8E000000) have shown intermittent write
-# corruption during long disk loads.
+# verification + FIT parse.  0x82000000 is 32 MB into the cached DDR window
+# at 0x80000000, which is 1 GB wide - 0xC0000000 up is the non-cached alias
+# onto the same DDR, so staging must stay below it.  It is clear of the
+# kernel destination below and 128 MB below the DTB region, which is the
+# headroom the staged-image bound further down depends on.
 # After the FIT is parsed:
 #   kernel is copied to 0x80200000 (FIT-internal "load")
 #   DTB is copied to WOLFBOOT_LOAD_DTS_ADDRESS (0x8A000000)
@@ -111,7 +116,7 @@ WOLFBOOT_RAMBOOT_MAX_SIZE=0x08000000
 
 # Use update_disk loader (partition A/B numbering instead of flash addresses).
 # BOOT_PART_A / BOOT_PART_B are 0-indexed GPT entry numbers.  GPT partitions
-# in our SD card layout (see tools/scripts/program-sdcard.sh):
+# in the SD card layout of docs/PolarFire.md:
 #   index 0 (parted "boot"   1 MiB - 33 MiB) -> active boot FIT
 #   index 1 (parted "update" 33 MiB - 65 MiB) -> inactive/update slot
 #   index 2 (parted "rootfs" 65 MiB - end)    -> Linux rootfs
@@ -122,28 +127,6 @@ CFLAGS_EXTRA+=-DBOOT_PART_B=1
 # Speed up disk partition read (512KB chunks - max DMA size)
 CFLAGS_EXTRA+=-DDISK_BLOCK_SIZE=0x80000
 
-# Disable SDMA on the Cadence SD4HC.  SDMA hangs silently at first
-# multi-block read on the Video Kit (Cadence boundary-cross bug).
-# Use PIO single-block reads instead.
-CFLAGS_EXTRA+=-DSDHCI_SDMA_DISABLED
-
-# Force single-block (CMD17) reads.  Multi-block PIO suffers a BRR
-# race on Arasan/Cadence-family controllers; single-block avoids it.
-CFLAGS_EXTRA+=-DSDHCI_FORCE_SINGLE_BLOCK_READ
-
-# Disk-load via PDMA staging.  On this board, CPU AXI writes to DDR
-# (cached or non-cached) do NOT reliably land at the address that
-# subsequent cached reads will fetch from -- empirical alias probe
-# showed CPU writes via the 0xC0000000 non-cached window are silently
-# dropped, and cached PIO writes appear to allocate L2 lines that are
-# never written back to DDR before the integrity-check read.
-#
-# Workaround: SDHCI PIO into a small L2 Scratch staging buffer, then
-# mpfs_pdma_memcpy() copies the block into DDR via the PDMA master.
-# PDMA-via-non-cached is the only AXI write path verified to land in
-# DDR (the same path used by mpfs_clear_bootup_cache_ways pre-fill).
-CFLAGS_EXTRA+=-DSDHCI_BLOCK_VIA_PDMA
-
 # Video Kit routes the SD slot's Card Detect (CD#) signal through the FPGA
 # fabric rather than MSSIO, so the SDHCI controller's hardware CI/CDPL
 # detection always reads 'no card' in M-mode (no fabric configuration).

config/examples/polarfire_mpfs250_m_qspi.config

@@ -43,14 +43,13 @@ ELF?=1
 # Stripped ELF is typically ~5KB.
 STRIP_ELF?=1
 
-# Watchdog timer configuration (default: disabled)
-#   When commented out, the WDT is disabled in hal_init() and re-enabled
-#   with the boot ROM default in hal_prepare_boot() before do_boot.
-#   Uncomment -DWATCHDOG to keep the WDT enabled with a generous timeout
-#   for the duration of wolfBoot. Verify is bounded at ~5s; default 30s
-#   avoids the need to pet the WDT during long ECDSA verify.
+# Watchdog timer configuration
+#   The MSS watchdogs are armed by the bitstream and count whatever this
+#   is set to; wolfBoot refreshes all five in hal_init() and again in
+#   hal_prepare_boot().  There is no timeout to set and no way to disarm
+#   them from software: the window is a bitstream property (~28.6 s), and
+#   verify is bounded at ~5 s, so nothing has to pet it mid-signature.
 #CFLAGS_EXTRA+=-DWATCHDOG
-#CFLAGS_EXTRA+=-DWATCHDOG_TIMEOUT_MS=30000
 
 OPTIMIZATION_LEVEL=1