[dgarske]

Description

hal/samr21.c is a SAM D21 HAL, clocked for a SAMD21G18A at 48MHz, but nothing could reach it: no example config, no docs, no CI build.

Adds config/examples/samd21.config and samd21_j18.config for the 128KB/16KB and 256KB/32KB parts, a SERCOM console, a docs/Targets.md section, CI jobs, and wolfBoot_success() in the test app so an A/B update confirms instead of rolling back. WOLFBOOT_RAM_SIZE is now a linker substitution, as the script hardcoded 16KB and capped the 32KB parts.

Both layouts use a 32KB bootloader region, because the NVMCTRL BOOTPROT fuse protects 8KB, 16KB or 32KB and nothing in between: any other boundary either leaves the bootloader writable or pushes the protected region into the boot partition, where it would block the swap.

HAL fixes:

• hal_init() and hal_prepare_boot() cleared APBBMASK.NVMCTRL, set out of reset, gating the flash controller's clock off before any write or erase.
• PAC_WP_NVMCTL was the DSU bit; NVMCTRL is peripheral 34 vs PAC1's base 32, so bit 2.
• hal_flash_write() issued one page-write per transfer; now sets CTRLB.MANW and commits each page.
• Write and erase always returned success; they now report NVMCTRL.STATUS errors.

Testing

Not validated on hardware; the console pinout is from the Xplained Pro schematic. Both configs build, and unit-samr21-erase-advance and unit-flash-write-samr21 cover the erase stride, a multi-page write and the error returns.