The aim of the assignment is to design a simple combination lock using VHDL and synchronous design techniques, and to implement your design on the FPGA board. The user interface will be simple and based on use of the push buttons, slider switches, LEDs and 7segment display on the FPGA board.
The aim of the assignment is to design a combination lock with VHDL, which could input, verify and reset the passcode and set a new passcode of any suitable lengthy. With the 7-segment display, the combination lock will be more convenient for the user, the combination lock will display the number (convert binary digit to decimal digit) and the result is correct(OK) or error(Err).