RTL-to-GDSII Physical Design Implementation of PicoRV32a RISC-V Processor
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Complete RTL-to-GDSII physical design implementation of the PicoRV32a RISC-V processor using the OpenLANE automated EDA flow on the Google SkyWater 130nm (Sky130) open-source PDK.
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The project covers the full digital design flow from RTL synthesis through to fabrication-ready GDSII generation — including integration of a custom-designed standard cell (sky130_vsdinv), timing closure via ECOs, and post-route parasitic extraction.
| Category | Tool / Technology |
|---|---|
| Flow Manager | OpenLANE |
| PDK | Sky130 (sky130A) |
| Design | PicoRV32a RISC-V Core |
| Synthesis | Yosys + ABC |
| Static Timing Analysis | OpenSTA |
| Placement & CTS | OpenROAD, TritonCTS |
| Routing | TritonRoute |
| Layout & DRC | Magic VLSI |
| Parasitic Extraction | SPEF Extractor |
| SPICE Simulation | Ngspice |
| LVS | Netgen |
| HDL | Verilog |
| OS | Ubuntu Linux |
| Stage | Tool | Description | Status |
|---|---|---|---|
| RTL Synthesis | Yosys + ABC | Verilog → gate-level netlist, cell mapping | ✅ Complete |
| Floorplan & Power | OpenROAD | Die area, core utilisation, IO placement | ✅ Complete |
| Placement | OpenROAD | Standard cell placement, congestion optimisation | ✅ Complete |
| Custom Cell Design | Magic, Ngspice | sky130_vsdinv — layout, SPICE, LEF extraction | ✅ Complete |
| Timing ECO | OpenSTA | Setup/hold fixing, cell upsizing, slack closure | ✅ Complete |
| Clock Tree Synthesis | TritonCTS | Clock insertion, skew minimisation, buffer sizing | ✅ Complete |
| Power Distribution | OpenROAD | PDN — rings, straps, standard cell rails | ✅ Complete |
| Routing | TritonRoute | Global + detailed routing, DRC compliance | ✅ Complete |
| Parasitic Extraction | SPEF Extractor | Post-route RC parasitics for sign-off STA | ✅ Complete |
| Sign-off STA | OpenSTA | Setup and hold verified with real clock model | ✅ Complete |
| GDSII Generation | Magic | Final layout — fabrication ready | ✅ Complete |
| Metric | Value |
|---|---|
| Design | PicoRV32a RISC-V Processor |
| Technology Node | 130nm (Sky130 PDK) |
| Clock Period | 24.73 ns |
| Clock Frequency | 40.44 MHz |
| Total Cell Count | 17,108 |
| Flop Ratio | 9.43% (1,613 flip-flops) |
| Chip Area | 181,510.33 µm² |
| Die Area | 731.18 × 741.90 µm |
| Core Area | 719.90 × 718.08 µm |
| Metal Layers | 6 — li1, met1, met2, met3, met4, met5 |
| Custom Cell Integrated | sky130_vsdinv (Custom Inverter) |
| Post-Synthesis WNS | 0.00 ns |
| Post-Synthesis TNS | 0.00 ns |
| Post-Route WNS | 0.00 ns |
| Post-Route TNS | 0.00 ns |
| Routing Runtime | 25 minutes 21 seconds |
| DRC Violations | 0 |
| LVS Status | Clean |
| GDSII | Generated — Fabrication Ready |
📁 Project-DigitalVLSI-SoC-Design-Planning
├── 📁 01 : Synthesis → RTL synthesis, netlist, cell mapping
├── 📁 02 : Floorplan → Floorplan, IO placement, Magic layout
├── 📁 03 : Placement → Congestion-aware placement
├── 📁 04 : Custom cell → sky130_vsdinv design, SPICE, LEF
├── 📁 05 : Timing closure → Slack fixing, OpenSTA, ECO
├── 📁 06 : CTS → CTS run, verification, real clock
├── 📁 07 : PDN → Power distribution network
├── 📁 08 : Routing → TritonRoute global and detailed routing
├── 📁 09 : GDSII → SPEF extraction, final GDSII
└── 📄 README.md
01 — Synthesis | Yosys ABC OpenSTA
RTL synthesised using Yosys with technology mapping to Sky130 standard cells via ABC. OpenLANE environment initialised, design hierarchy verified, and synthesis reports analysed for cell utilisation, area, and initial timing slack. Gate-level netlist generated as foundation for physical implementation.
02 — Floorplan | OpenROAD Magic
Die area and core utilisation defined. Standard cell rows generated and aligned with Sky130 routing tracks. IO pins placed and verified. Layout opened in Magic for visual inspection of row orientation, spacing, and pin accessibility.
03 — Placement | OpenROAD RePlAce
Congestion-aware global placement using RePlAce. Standard cells placed and legalised within core area. Placement density and routing resource availability verified before proceeding to CTS.
04 — Custom Standard Cell | Magic Ngspice Sky130
Custom inverter cell sky130_vsdinv designed from scratch in Magic following Sky130 DRC rules. SPICE netlist extracted and simulated using Ngspice. Timing characterised using Sky130 Liberty files. LEF extracted and integrated into OpenLANE flow — verified post-synthesis and post-CTS.
05 — Timing Closure | OpenSTA ECO
Post-synthesis timing violations identified using OpenSTA. Setup slack resolved through synthesis strategy tuning — SYNTH_STRATEGY, SYNTH_BUFFERING, SYNTH_SIZING parameters adjusted. Manual ECOs performed by cell upsizing on critical paths. TNS and WNS verified toward zero before CTS.
06 — Clock Tree Synthesis | TritonCTS OpenSTA
Clock tree built using TritonCTS. Clock buffers inserted to balance load and minimise skew across all flip-flops. Buffer drive strength experimented — impact on slew, skew, area, and power analysed. Real clock propagation model applied and hold slack verified post-CTS.
07 — Power Distribution Network | OpenROAD Magic
PDN generated using gen_pdn. Power rings, straps, and standard cell rails built across die. Via connectivity verified at all strap intersections. Custom inverter rail connectivity confirmed in Magic. Design prepared for signal routing with full power integrity.
08 — Routing | FastRoute TritonRoute
Global routing performed using FastRoute — approximate paths planned across G-cell grid. Detailed routing completed using TritonRoute — exact metal shapes and vias placed with full DRC compliance. Iterative optimisation passes reduced violations to zero.
09 — GDSII Generation | SPEF Extractor Magic Netgen
Post-route parasitic extraction performed using SPEF Extractor — RC wire data generated for all nets. Final sign-off STA executed with real parasitics — setup and hold slack both positive. GDSII streamed out using Magic — fabrication-ready layout verified DRC-clean.
| Custom Cell Design | vsdstdcelldesign by Nickson Jose |
|---|---|
| PDK | Google SkyWater Sky130 PDK |
| EDA Flow | OpenLANE by efabless |
This project is licensed under the Apache License 2.0 — as used by the OpenLANE flow developed by efabless corporation.
| Author | Preetham SK |
|---|---|
| Program | NASSCOM FutureSkills Prime — VSD (VLSI System Design) |
| linkedin.com/in/preethamsk16 | |
| GitHub | github.com/PreethamSK163 |
| Portfolio | preethamsk163.github.io |
| preethamsk163@gmail.com |