This repository contains all major projects completed as part of the EECS 4612: Digital VLSI Design course at York University. The projects showcase the complete ASIC design flow — from RTL design to GDSII layout — using industry-grade tools like Cadence Genus, Innovus, and Virtuoso.

SPEAR – Single Neuron Hardware Accelerator Engine. A collaborative hardware project combining full custom ASIC design and FPGA-based validation. The CHIP team designed a perceptron accelerator from RTL to GDSII using Synopsys tools and TSMC 28nm. The FPGA team built a working test platform on DE10-Lite. Developed with mentorship and technical suppo

Complete design of RISC-V SoC from basic RTL to GDSII

CNN accelerator datapath components

Complete ASIC design flow for a Simple Inverter — from RTL (Verilog) to GDSII — using the OpenLane toolchain and the SkyWater 130nm PDK (sky130)

End-to-end RTL to GDSII ASIC physical design implementation at 28nm using Synopsys DC and ICC2 with full timing closure and DRC clean signoff.

Dynamic reconfigurable binary multiplier using quadrant decomposition and adaptive row bypassing for scalable, low-power operation. Designed in Verilog and implemented on TSMC 180nm/90nm using Cadence tools. Published Indian patent (202541080342).

An RTL-to-GDSII ASIC Flow Project Design, simulate, synthesize, and layout a full 1×8 demux for 8-bit data — all the way from Verilog to GDSII.

Underlying EDA toolchain engine for the ChipForAll project.

Full RTL-to-GDSII implementation of an 8-bit registered adder using SkyWater 130nm PDK and open-source EDA tools

complete walkthrough of the vlsi design process for an equation Y = 4^X development to sta, using synopsys

A hands-on implementation of physical design for a Serial Peripheral Interface (SPI) controller — progressing from RTL Verilog through synthesis, placement, static timing analysis, routing, DRC, LVS, and GDSII generation using the open-source Qflow EDA toolchain with OSU018 standard cell library.

RTL-to-GDSII implementation of a 4-bit ALU using Cadence Genus and Innovus (ASIC Design Flow)

RTL-to-GDSII physical design flow of PicoRV32a RISC-V processor using OpenLANE and Sky130 PDK. Completed under NASSCOM FutureSkills Prime program. Synthesis, floorplan, placement, CTS, routing, DRC/LVS clean, GDSII generated.