arch/arm/src/stm32h7: add 4-bit wide bus support for MMC/eMMC cards

[13022591351]

Summary

The STM32H7 SDMMC driver never programs the WIDBUS bits for MMC cards:
stm32_widebus() only records the requested state and the MMC transfer
clock preset STM32_SDMMC_CLKCR_MMCXFR is hardwired to WIDBUS_D1. When the
mmcsd layer switches an eMMC device to 4-bit mode via CMD6 (MMC_SWITCH),
the host stays in 1-bit mode and all subsequent data transfers fail with
a bus width mismatch.

Program the WIDBUS bits in stm32_widebus() so the host bus width follows
the card, and add a CLOCK_MMC_TRANSFER_4BIT clock preset.

Impact

• arch/arm/src/stm32h7: eMMC devices now actually operate in 4-bit mode;
  SD card behavior is unchanged.
• include/nuttx/sdio.h: CLOCK_MMC_TRANSFER_4BIT appended to enum
  sdio_clock_e (existing values are not renumbered).
• stm32f7/stm32l4 share the same stm32_widebus() pattern and may need the
  same change; left for follow-up PRs as I can only test H7 hardware.

Testing

Custom STM32H743 board with eMMC (PX4 V6X derived design), same change
verified via a backport to the PX4 NuttX 10.3 branch:
sd_bench sequential write ~4.0 MB/s, sequential read ~6.3 MB/s.

[github-actions]

MemBrowse Memory Report

No memory changes detected for:

• arduino-mega2560
• hifive1-revb
• mirtoo
• qemu-armv8a
• qemu-intel64
• rx65n-rsk2mb
• s698pm-dkit
• stm32-nucleo-f103rb

[acassis]

@raiden00pl PTAL

@13022591351 Do you know if other STM32 family (F7, H5, etc) also require this improvement?

[linguini1]

Awesome! Do you have any log output from SD bench you can attach?

[13022591351]

Awesome! Do you have any log output from SD bench you can attach?

nsh> ver all
HW arch:
PX4 git-hash: a5e191b7f5f2744b74a5aae0782eed390b8c6dd5
PX4 version: 1.15.2 0 (17760768)
PX4 git-branch: v1.15.2-dev
OS: NuttX
OS version: Release 11.0.0 (184549631)
OS git-hash: 53795e88496a505c6fe679de637a2e3f6ba500f7
Build datetime: Jul 16 2026 13:38:06
Build uri: localhost
Build variant: default
Toolchain: GNU GCC, 10.3.1 20210824 (release)
PX4GUID: 000600000000363836363033510500200047
MCU: STM32H7[4|5]xxx, rev. V
nsh> sd_bench -v
INFO [sd_bench] Using block size = 4096 bytes, sync=0
INFO [sd_bench]
INFO [sd_bench] Testing Sequential Write Speed...
INFO [sd_bench] Run 0: 4003.32 KB/s, max write time: 9 ms (= 444.44 KB/s), fsync: 2 ms
INFO [sd_bench] Run 1: 4135.69 KB/s, max write time: 7 ms (= 571.43 KB/s), fsync: 4 ms
INFO [sd_bench] Run 2: 4146.69 KB/s, max write time: 8 ms (= 500.00 KB/s), fsync: 3 ms
INFO [sd_bench] Run 3: 4135.73 KB/s, max write time: 8 ms (= 500.00 KB/s), fsync: 3 ms
INFO [sd_bench] Run 4: 4157.10 KB/s, max write time: 7 ms (= 571.43 KB/s), fsync: 3 ms
INFO [sd_bench] Avg : 4115.71 KB/s
INFO [sd_bench] Overall max write time: 9 ms
INFO [sd_bench]
INFO [sd_bench] Testing Sequential Read Speed of 10309 blocks
INFO [sd_bench] Run 0: 6301.92 KB/s, max read/verify time: 2 ms (=2000.00 KB/s)
INFO [sd_bench] Run 1: 6268.30 KB/s, max read/verify time: 2 ms (=2000.00 KB/s)
INFO [sd_bench] Run 2: 6250.49 KB/s, max read/verify time: 2 ms (=2000.00 KB/s)
INFO [sd_bench] Run 3: 6270.58 KB/s, max read/verify time: 1 ms (=4000.00 KB/s)
INFO [sd_bench] Avg : 6273.31 KB/s 10309 blocks read and verified

[13022591351]

@raiden00pl PTAL

@13022591351 Do you know if other STM32 family (F7, H5, etc) also require this improvement?

Next Monday I'll analyze it using LLM tools. It's possible that even after merging, 4-bit eMMC still won't be implemented. I'm developing and testing on the PX4/NuttX branch, but the PX4 commit process requires distributed execution. For a complete reproduction of 4-bit eMMC on the H7 platform, please refer to https://github.com/13022591351/PX4-NuttX/tree/pr-fix-stm32h7-emmc_4wire

After merging this commit, I will continue to check the relevant code in drivers/mmcsd/mmcsd_sdio.c.