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arch/arm/src/stm32h7: add 4-bit wide bus support for MMC/eMMC cards #19462

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arch/arm/src/stm32h7: add 4-bit wide bus support for MMC/eMMC cards #19462

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27 changes: 27 additions & 0 deletions arch/arm/src/stm32h7/stm32_sdmmc.c
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Original file line number Diff line number Diff line change
Expand Up @@ -210,6 +210,10 @@
STM32_SDMMC_CLKCR_EDGE | \
STM32_SDMMC_CLKCR_PWRSAV | \
STM32_SDMMC_CLKCR_WIDBUS_D1)
#define STM32_SDMMC_CLKCR_MMCXFR4 (STM32_SDMMC_MMCXFR_CLKDIV | \
STM32_SDMMC_CLKCR_EDGE | \
STM32_SDMMC_CLKCR_PWRSAV | \
STM32_SDMMC_CLKCR_WIDBUS_D4)
#define STM32_SDMMC_CLCKR_SDXFR (STM32_SDMMC_SDXFR_CLKDIV | \
STM32_SDMMC_CLKCR_EDGE | \
STM32_SDMMC_CLKCR_PWRSAV | \
Expand Down Expand Up @@ -2045,7 +2049,24 @@ static sdio_statset_t stm32_status(struct sdio_dev_s *dev)
static void stm32_widebus(struct sdio_dev_s *dev, bool wide)
{
struct stm32_dev_s *priv = (struct stm32_dev_s *)dev;
uint32_t regval;

priv->widebus = wide;

regval = sdmmc_getreg32(priv, STM32_SDMMC_CLKCR_OFFSET);
regval &= ~STM32_SDMMC_CLKCR_WIDBUS_MASK;

if (wide)
{
regval |= STM32_SDMMC_CLKCR_WIDBUS_D4;
regval &= ~STM32_SDMMC_CLKCR_PWRSAV;
}
else
{
regval |= STM32_SDMMC_CLKCR_WIDBUS_D1;
}

sdmmc_putreg32(priv, regval, STM32_SDMMC_CLKCR_OFFSET);
}

/****************************************************************************
Expand Down Expand Up @@ -2089,6 +2110,12 @@ static void stm32_clock(struct sdio_dev_s *dev, enum sdio_clock_e rate)
clckr = STM32_SDMMC_CLKCR_MMCXFR;
break;

/* Enable in MMC wide (4-bit) operation clocking */

case CLOCK_MMC_TRANSFER_4BIT:
clckr = STM32_SDMMC_CLKCR_MMCXFR4;
break;

/* SD normal operation clocking (wide 4-bit mode) */

case CLOCK_SD_TRANSFER_4BIT:
Expand Down
5 changes: 3 additions & 2 deletions include/nuttx/sdio.h
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Original file line number Diff line number Diff line change
Expand Up @@ -942,9 +942,10 @@ enum sdio_clock_e
{
CLOCK_SDIO_DISABLED = 0, /* Clock is disabled */
CLOCK_IDMODE, /* Initial ID mode clocking (<400KHz) */
CLOCK_MMC_TRANSFER, /* MMC normal operation clocking */
CLOCK_MMC_TRANSFER, /* MMC normal operation clocking (narrow 1-bit mode) */
CLOCK_SD_TRANSFER_1BIT, /* SD normal operation clocking (narrow 1-bit mode) */
CLOCK_SD_TRANSFER_4BIT /* SD normal operation clocking (wide 4-bit mode) */
CLOCK_SD_TRANSFER_4BIT, /* SD normal operation clocking (wide 4-bit mode) */
CLOCK_MMC_TRANSFER_4BIT /* MMC normal operation clocking (wide 4-bit mode) */
};

/* Event set. A uint8_t is big enough to hold a set of 8-events. If more
Expand Down
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