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- Number of changes have been made in order to more accurately replicate instructions in a RISC-V CPU, mostly noticeably there is a new top level model, CPU_Core, which incorporates the ALU, ALU_Control, and register_file. This way there are two register addresses with a given value, which if write enable is high, are then set to A and B. As previously I was just setting A and B directly, I still have to have them read and packed as 32 bit instructions as that is more accurate. CPU_CORE_TB was able to pass 100% of the tests scenarios in it.
- I also took the time to make a module for all the parameters for Funct3,Funct7, and the opcodes. As it saves time having to look them up and makes the code more readable.
## 12/9/23
- Apologies for long break since last post but significant progress had been made. The ALU has now been fully complete. I switched from using a Dadda multiplier and instead am now using a more simple Array style multiplier as well as a long division based divider. These are both slower and less efficent methods but the time sink was immenese and I felt it might be more useful to move onto other tasks. I have verified all components and the ALU functionality is now fully in place.
- To simulate Quartus was used as part of the problems faced prior was the schools Modelsim not being upto snuff and requiring significant time and effort on my part, so I ended up installing Quartus on my local machine which proved much easier.
- Now that the ALU is largely complete I wil move onto working on the register file.
-Made significant headway for Dadda Multiplier, did not occur to me that I substantially reduce complexity for the non start/end cases by using a single generate block with current and next arrays. This alone reduced the number of lines by 75%.
-I also wrote an absolute module in order to check which indexes would need to be evaluated. I also made changes to multiple of my other modules, as I made some very silly errors, I think my focus on the Dadda Multiplier made some of its requisite modules less of a priority and coming back I was able to discover some obvious changes were needed.
-Apologies for the gap in updates but hasn't been too much significant to report until today.
-Created module that is able to do a Dadda tree, required a signifcant amount of effort.
-Working on documentation on how I did this in great detail once done since I could find little good information about Dadda Multiplier's implementation in System Verilog, only others on Github were done statically
-Was not able to make enough progress yet to get multiplication set up but tree itself is set up. Goes without saying that it is untested.
-Created half and full adder modules to use for the reduction steps of the Dadda Multiplier.
-Created additional tests for Adder, Subtractor to do a sequence of randomized tests and check with golden model. This then calculates the total number of tests correct out of the total done, meaning that the user does not have to check each test manually
## 11/16/23
-Implemented working CLA and Subtraction module. Took a good amount of checking, many changes made including those to assign statements, movement of instantiations for CLA, Subtraction from ALU_TB to ALU.sv in order to improve TB readibility.
## 11/15/23
-Initial Module, contains a tested ALU and control setup that allows for the correct basic arthimetic operation(addition,subtraction,multiplication,division,set less than) based on the inputted opcode, funct 3, funct 7.
-Untested module for Carry Look Ahead Adder(CLA) and Subtraction module