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- Added a new `rdHold` field to the `RegType` record in `AxiResize.vhd` to buffer read data from the master. - Updated initialization of `rdHold` to ensure proper reset behavior. - Implemented logic to manage read data transfer, allowing for smoother handling of read operations and preventing dependency on the live master-side bus. - Adjusted conditions for data movement and validity checks to incorporate the new read hold mechanism, improving overall data integrity during transactions.
# Conflicts: # docs/_meta/rtl_regression_handoff.md # docs/_meta/rtl_regression_progress.md
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@thatweaver I added you as a reviewer as https://github.com/slaclab/l2si-drp is the only slaclab repo that uses surf.AxiResize right now |
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Pull request overview
Fixes an AXI4 read resizing issue in AxiResize when the slave-side data width is smaller than the master-side width (e.g., 32-bit slave to 64-bit master), by buffering a master-side read beat before emitting multiple narrower downstream beats. The accompanying cocotb regression is updated to enable the previously-xfailed upsize case now that the RTL bug is addressed.
Changes:
- Add a read “hold” register (
rdHold) inAxiResizeto decouple narrow-beat slicing from the live master read-data bus. - Update the downsize read-data slicing logic to use the buffered beat and preserve
rid/rresp/rlastacross slices. - Remove the
xfailmarker for the 32-bit → 64-bit upsize regression case intest_AxiResize.py.
Reviewed changes
Copilot reviewed 2 out of 2 changed files in this pull request and generated 1 comment.
| File | Description |
|---|---|
axi/axi4/rtl/AxiResize.vhd |
Buffers accepted wide read beats and serves narrow slices from the buffer to fix the upsize read path. |
tests/axi/axi4/test_AxiResize.py |
Enables the upsize parameter case by removing the prior xfail. |
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Pull request overview
Copilot reviewed 2 out of 2 changed files in this pull request and generated no new comments.
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Description
Fix the AXI read upsize path in
AxiResizeby buffering accepted wide read data before slicing it into narrower downstream beats, and enable the previously xfailed 32-bit to 64-bit resize test now that the RTL bug is fixed.Details
The read path now stores an accepted master-side beat in a hold register and serves subsequent slave-width slices from that buffered value instead of depending on the live master bus after the initial handshake. This preserves
rid,rresp, andrlastcorrectly across the full sequence of downsliced responses.The test update removes the
xfailmarker from the upsize regression case intest_AxiResize.py, since the bug is now fixed.Related
#1386 must be merged first.