feat(spacemit): add TCM memory barrier support#11
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Pull request overview
Adds a compile-time guard for Spacemit RISC-V64 TCM “memory barrier” operations around thread-affinity setup/teardown, presumably to make the wait/release behavior optional.
Changes:
- Wrap
spine_mem_pool_tcm_mem_wait()inggml_backend_cpu_riscv64_spacemit_set_numa_thread_affinity()with#ifdef GGML_ENABLE_TCM_MEM_BARRIER. - Wrap
spine_mem_pool_tcm_mem_release()inggml_backend_cpu_riscv64_spacemit_clear_numa_thread_affinity_threaded()with the same macro.
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| if (ggml::cpu::riscv64_spacemit::tls_context.tcm_buffer != nullptr) { | ||
| void * rt = | ||
| ggml::cpu::riscv64_spacemit::spine_mem_pool_tcm_mem_wait(ggml::cpu::riscv64_spacemit::tls_context.cpu_id); | ||
| if (rt == nullptr) { | ||
| GGML_ABORT("wait tcm buffer failed for cpu_id: %d", ggml::cpu::riscv64_spacemit::tls_context.cpu_id); |
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| auto rt = ggml::cpu::riscv64_spacemit::spine_mem_pool_tcm_mem_release( | ||
| ggml::cpu::riscv64_spacemit::tls_context.cpu_id); | ||
| if (rt != 0) { | ||
| GGML_ABORT("release tcm buffer failed for cpu_id: %d", ggml::cpu::riscv64_spacemit::tls_context.cpu_id); | ||
| } | ||
| } |
| ggml::cpu::riscv64_spacemit::global_spine_env_info.tcm_blk_size; | ||
| } | ||
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| #ifdef GGML_ENABLE_TCM_MEM_BARRIER |
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