A Bare-Metal PIM-HBM Hardware Co-Design Core Engine exploring Register-Level MUX Virtualization to mitigate NCCL All-to-All communication stalls.
-
Updated
Jul 24, 2026 - Python
A Bare-Metal PIM-HBM Hardware Co-Design Core Engine exploring Register-Level MUX Virtualization to mitigate NCCL All-to-All communication stalls.
Software-Defined PIM-HBM Bypass Infrastructure. 0ns JAX/XLA memory view fusion with real-time asynchronous NCCL collective fault-scanning & no-recompile Mux hot-swapping.
Add a description, image, and links to the memory-bypass topic page so that developers can more easily learn about it.
To associate your repository with the memory-bypass topic, visit your repo's landing page and select "manage topics."